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d9386dc8e9
Drop backported patches already included in 6.6 and refresh the rest to apply. Signed-off-by: Robert Marko <robimarko@gmail.com>
122 lines
2.4 KiB
Diff
122 lines
2.4 KiB
Diff
From 04d2fc6a551bbd972a6428059b45ce79cb9de9d7 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Fri, 6 May 2022 22:38:24 +0200
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Subject: [PATCH] arm64: dts: qcom: ipq8074: add QFPROM fuses
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Add the QFPROM node and CPR fuses.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 107 ++++++++++++++++++++++++++
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1 file changed, 107 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -349,6 +349,106 @@
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reg = <0x000a4000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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+
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+ cpr_efuse_speedbin: speedbin@125 {
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+ reg = <0x125 0x1>;
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+ bits = <0 3>;
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+ };
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+
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+ cpr_efuse_boost_cfg: boost_cfg@125 {
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+ reg = <0x125 0x1>;
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+ bits = <3 3>;
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+ };
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+
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+ cpr_efuse_misc_volt_adj: misc_volt_adj@125 {
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+ reg = <0x125 0x1>;
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+ bits = <3 3>;
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+ };
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+
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+ cpr_efuse_boost_volt: boost_volt@126 {
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+ reg = <0x126 0x1>;
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+ bits = <6 1>;
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+ };
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+
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+ cpr_efuse_revision: revision@23e {
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+ reg = <0x23e 0x1>;
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+ bits = <5 3>;
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+ };
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+
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+ cpr_efuse_ro_sel0: rosel0@249 {
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+ reg = <0x249 0x1>;
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+ bits = <0 4>;
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+ };
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+
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+ cpr_efuse_ro_sel1: rosel1@248 {
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+ reg = <0x248 0x1>;
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+ bits = <4 4>;
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+ };
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+
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+ cpr_efuse_ro_sel2: rosel2@248 {
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+ reg = <0x248 0x2>;
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+ bits = <0 4>;
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+ };
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+
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+ cpr_efuse_ro_sel3: rosel3@249 {
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+ reg = <0x249 0x1>;
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+ bits = <4 4>;
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+ };
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+
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+ cpr_efuse_init_voltage0: ivoltage0@23a {
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+ reg = <0x23a 0x1>;
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+ bits = <2 6>;
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+ };
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+
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+ cpr_efuse_init_voltage1: ivoltage1@239 {
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+ reg = <0x239 0x2>;
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+ bits = <4 6>;
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+ };
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+
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+ cpr_efuse_init_voltage2: ivoltage2@238 {
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+ reg = <0x238 0x2>;
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+ bits = <6 6>;
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+ };
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+
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+ cpr_efuse_init_voltage3: ivoltage3@238 {
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+ reg = <0x238 0x1>;
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+ bits = <0 6>;
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+ };
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+
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+ cpr_efuse_quot0: quot0@244 {
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+ reg = <0x244 0x2>;
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+ bits = <0 12>;
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+ };
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+
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+ cpr_efuse_quot1: quot1@242 {
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+ reg = <0x242 0x2>;
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+ bits = <4 12>;
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+ };
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+
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+ cpr_efuse_quot2: quot2@241 {
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+ reg = <0x241 0x2>;
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+ bits = <0 12>;
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+ };
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+
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+ cpr_efuse_quot3: quot3@245 {
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+ reg = <0x245 0x2>;
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+ bits = <4 12>;
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+ };
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+
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+ cpr_efuse_quot0_offset: quot0_offset@23d {
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+ reg = <0x23d 0x2>;
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+ bits = <6 7>;
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+ };
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+
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+ cpr_efuse_quot1_offset: quot1_offset@23c {
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+ reg = <0x23c 0x2>;
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+ bits = <7 7>;
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+ };
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+
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+ cpr_efuse_quot2_offset: quot2_offset@23c {
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+ reg = <0x23c 0x1>;
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+ bits = <0 7>;
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+ };
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};
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prng: rng@e3000 {
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