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Build on at leasst x86/64 failed without adding the new ksym: CONFIG_PCP_BATCH_SCALE_MAX=5 According to www.kernelconfig.io[1], this option seems to apply to all arches so I placed it in target/linux/generic/config-6.6 Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.45 Removed upstreamed: generic/backport-6.6/719-v6.11-net-phy-realtek-add-support-for-RTL8366S-Gigabit-PHY.patch[2] All other patches automatically rebased. 1. https://www.kernelconfig.io/config_pcp_batch_scale_max?q=&kernelversion=6.10.3&arch=x86 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.45&id=b45cbfa204b2a0985eb85dcb33d51714ee089bb9 Build system: x86/64 Build-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3 Run-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3 Signed-off-by: John Audia <therealgraysky@proton.me> Link: https://github.com/openwrt/openwrt/pull/16144 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
44 lines
1.5 KiB
Diff
44 lines
1.5 KiB
Diff
From fb1f6850be00d8dd8a54017be4c1336e224069ac Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Wed, 16 Nov 2022 22:26:25 +0100
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Subject: [PATCH] arm64: dts: qcom: ipq8074: use msi-parent for PCIe
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Instead of hardcoding the IRQ, simply use msi-parent instead.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 +++-----
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1 file changed, 3 insertions(+), 5 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -757,7 +757,7 @@
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reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
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ranges = <0 0xb00a000 0xffd>;
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- v2m@0 {
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+ gic_v2m0: v2m@0 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x0 0xffd>;
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@@ -870,8 +870,7 @@
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ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
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<0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
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- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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- interrupt-names = "msi";
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+ msi-parent = <&gic_v2m0>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 0 142
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@@ -932,8 +931,7 @@
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ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */
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<0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
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- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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- interrupt-names = "msi";
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+ msi-parent = <&gic_v2m0>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 0 75
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