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b519908e84
Now that 3.13 will be EOL soon, switch to 3.14. Known issues: * 74x164 is not available because upstream dropped non-DT support * jffs2 breaks with SMP Unknown issues: * probably plenty Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 40380
78 lines
2.5 KiB
Diff
78 lines
2.5 KiB
Diff
From c50acd37b425a8a907a6f7f93aa2e658256e79ce Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Sat, 7 Dec 2013 14:08:36 +0100
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Subject: [PATCH 40/53] MIPS: BCM63XX: add a new cpu variant helper
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---
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arch/mips/bcm63xx/cpu.c | 10 ++++++++++
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 18 ++++++++++++++++++
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2 files changed, 28 insertions(+)
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--- a/arch/mips/bcm63xx/cpu.c
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+++ b/arch/mips/bcm63xx/cpu.c
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@@ -27,6 +27,8 @@ EXPORT_SYMBOL(bcm63xx_irqs);
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u16 bcm63xx_cpu_id __read_mostly;
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EXPORT_SYMBOL(bcm63xx_cpu_id);
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+static u32 bcm63xx_cpu_variant __read_mostly;
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+
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static u8 bcm63xx_cpu_rev;
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static unsigned int bcm63xx_cpu_freq;
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static unsigned int bcm63xx_memory_size;
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@@ -99,6 +101,13 @@ static const int bcm6368_irqs[] = {
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};
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+u32 bcm63xx_get_cpu_variant(void)
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+{
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+ return bcm63xx_cpu_variant;
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+}
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+
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+EXPORT_SYMBOL(bcm63xx_get_cpu_variant);
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+
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u8 bcm63xx_get_cpu_rev(void)
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{
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return bcm63xx_cpu_rev;
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@@ -334,6 +343,7 @@ void __init bcm63xx_cpu_init(void)
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/* read out CPU type */
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tmp = bcm_readl(chipid_reg);
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bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
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+ bcm63xx_cpu_variant = bcm63xx_cpu_id;
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bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
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switch (bcm63xx_cpu_id) {
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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@@ -19,6 +19,7 @@
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#define BCM6368_CPU_ID 0x6368
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void __init bcm63xx_cpu_init(void);
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+u32 bcm63xx_get_cpu_variant(void);
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u8 bcm63xx_get_cpu_rev(void);
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unsigned int bcm63xx_get_cpu_freq(void);
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@@ -82,6 +83,23 @@ static inline u16 __pure bcm63xx_get_cpu
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#define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
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#define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
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+#define BCMCPU_VARIANT_IS_3368() \
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+ (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID)
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+#define BCMCPU_VARIANT_IS_6328() \
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+ (bcm63xx_get_cpu_variant() == BCM6328_CPU_ID)
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+#define BCMCPU_VARIANT_IS_6338() \
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+ (bcm63xx_get_cpu_variant() == BCM6338_CPU_ID)
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+#define BCMCPU_VARIANT_IS_6345() \
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+ (bcm63xx_get_cpu_variant() == BCM6345_CPU_ID)
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+#define BCMCPU_VARIANT_IS_6348() \
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+ (bcm63xx_get_cpu_variant() == BCM6348_CPU_ID)
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+#define BCMCPU_VARIANT_IS_6358() \
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+ (bcm63xx_get_cpu_cariant() == BCM6358_CPU_ID)
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+#define BCMCPU_VARIANT_IS_6362() \
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+ (bcm63xx_get_cpu_variant() == BCM6362_CPU_ID)
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+#define BCMCPU_VARIANT_IS_6368() \
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+ (bcm63xx_get_cpu_variant() == BCM6368_CPU_ID)
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+
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/*
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* While registers sets are (mostly) the same across 63xx CPU, base
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* address of these sets do change.
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