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52 lines
1.3 KiB
ArmAsm
52 lines
1.3 KiB
ArmAsm
/*
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* IFX Platform Dependent CPU Initializations
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* - for Danube
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*/
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#define IFX_EBU_BOOTCFG_DWORD \
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.word INFINEON_EBU_BOOTCFG; /* EBU init code, fetched during booting */ \
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.word 0x00000000; /* phases of the flash */
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#define IFX_MORE_RESERVED_VECTORS \
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XVECENT(romExcHandle,0x400); /* Int, CauseIV=1 */ \
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RVECENT(romReserved,129); \
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RVECENT(romReserved,130); \
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RVECENT(romReserved,131); \
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RVECENT(romReserved,132); \
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RVECENT(romReserved,133); \
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RVECENT(romReserved,134); \
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RVECENT(romReserved,135); \
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RVECENT(romReserved,136); \
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RVECENT(romReserved,137); \
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RVECENT(romReserved,138); \
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RVECENT(romReserved,139); \
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RVECENT(romReserved,140); \
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RVECENT(romReserved,141); \
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RVECENT(romReserved,142); \
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RVECENT(romReserved,143); \
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RVECENT(romExcHandle,0x480); /* EJTAG debug exception */
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#define IFX_RESET_PRECHECK \
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mfc0 k0, CP0_EBASE; \
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and k0, EBASEF_CPUNUM; \
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bne k0, zero, ifx_mips_handler_1; \
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nop;
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#define IFX_CPU_EXTRA_INIT \
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mfc0 k0, CP0_CONFIG, 7; \
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li k1, 0x04; \
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or k0, k1; \
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mtc0 k0, CP0_CONFIG, 7;
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#define IFX_CACHE_OPER_MODE \
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li t0, CONF_CM_CACHABLE_NO_WA;
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/*
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* Stop VCPU
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*/
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#define IFX_MIPS_HANDLER_1 \
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wait; \
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b ifx_mips_handler_1; \
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nop;
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