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4fd9028f44
These patches are written by Broadcom and will be in mainline Linux kernel soon. I had some problems to get them backported to kernel 4.1, so currently they are only available for 4.3. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> SVN-Revision: 47253
220 lines
7.7 KiB
Diff
220 lines
7.7 KiB
Diff
From d358480591b34d081806ecb5a9474930a4d59f8a Mon Sep 17 00:00:00 2001
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From: Jon Mason <jonmason@broadcom.com>
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Date: Thu, 15 Oct 2015 15:48:27 -0400
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Subject: [PATCH 46/50] clk: nsp: add clock support for Broadcom Northstar Plus
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SoC
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The Broadcom Northstar Plus SoC is architected under the iProc
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architecture. It has the following PLLs: ARMPLL, GENPLL, LCPLL0, all
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derived from an onboard crystal.
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Signed-off-by: Jon Mason <jonmason@broadcom.com>
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---
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drivers/clk/bcm/Makefile | 2 +
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drivers/clk/bcm/clk-nsp.c | 135 ++++++++++++++++++++++++++++++++++++
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include/dt-bindings/clock/bcm-nsp.h | 51 ++++++++++++++
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3 files changed, 188 insertions(+)
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create mode 100644 drivers/clk/bcm/clk-nsp.c
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create mode 100644 include/dt-bindings/clock/bcm-nsp.h
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--- a/drivers/clk/bcm/Makefile
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+++ b/drivers/clk/bcm/Makefile
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@@ -4,3 +4,5 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281
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obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o
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obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o
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obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o
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+obj-$(CONFIG_ARCH_BCM_NSP) += clk-nsp.o
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+obj-$(CONFIG_ARCH_BCM_5301X) += clk-nsp.o
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--- /dev/null
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+++ b/drivers/clk/bcm/clk-nsp.c
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@@ -0,0 +1,135 @@
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+/*
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+ * Copyright (C) 2015 Broadcom Corporation
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation version 2.
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+ *
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+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
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+ * kind, whether express or implied; without even the implied warranty
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+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/err.h>
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+#include <linux/clk-provider.h>
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+#include <linux/io.h>
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+#include <linux/of.h>
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+#include <linux/of_address.h>
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+
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+#include <dt-bindings/clock/bcm-nsp.h>
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+#include "clk-iproc.h"
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+
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+#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
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+
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+#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
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+ .pwr_shift = ps, .iso_shift = is }
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+
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+#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
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+ .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \
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+ .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
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+ .ka_width = kaw }
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+
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+#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
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+ .hold_shift = hs, .bypass_shift = bs }
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+
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+static void __init nsp_armpll_init(struct device_node *node)
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+{
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+ iproc_armpll_setup(node);
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+}
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+CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-armpll", nsp_armpll_init);
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+
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+static const struct iproc_pll_ctrl genpll = {
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+ .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL,
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+ .aon = AON_VAL(0x0, 1, 12, 0),
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+ .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
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+ .ndiv_int = REG_VAL(0x14, 20, 10),
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+ .ndiv_frac = REG_VAL(0x14, 0, 20),
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+ .pdiv = REG_VAL(0x18, 24, 3),
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+ .status = REG_VAL(0x20, 12, 1),
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+};
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+
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+static const struct iproc_clk_ctrl genpll_clk[] = {
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+ [BCM_NSP_GENPLL_PHY_CLK] = {
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+ .channel = BCM_NSP_GENPLL_PHY_CLK,
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+ .flags = IPROC_CLK_AON,
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+ .enable = ENABLE_VAL(0x4, 12, 6, 18),
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+ .mdiv = REG_VAL(0x18, 16, 8),
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+ },
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+ [BCM_NSP_GENPLL_ENET_SW_CLK] = {
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+ .channel = BCM_NSP_GENPLL_ENET_SW_CLK,
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+ .flags = IPROC_CLK_AON,
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+ .enable = ENABLE_VAL(0x4, 13, 7, 19),
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+ .mdiv = REG_VAL(0x18, 8, 8),
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+ },
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+ [BCM_NSP_GENPLL_USB_PHY_REF_CLK] = {
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+ .channel = BCM_NSP_GENPLL_USB_PHY_REF_CLK,
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+ .flags = IPROC_CLK_AON,
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+ .enable = ENABLE_VAL(0x4, 14, 8, 20),
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+ .mdiv = REG_VAL(0x18, 0, 8),
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+ },
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+ [BCM_NSP_GENPLL_IPROCFAST_CLK] = {
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+ .channel = BCM_NSP_GENPLL_IPROCFAST_CLK,
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+ .flags = IPROC_CLK_AON,
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+ .enable = ENABLE_VAL(0x4, 15, 9, 21),
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+ .mdiv = REG_VAL(0x1c, 16, 8),
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+ },
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+ [BCM_NSP_GENPLL_SATA1_CLK] = {
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+ .channel = BCM_NSP_GENPLL_SATA1_CLK,
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+ .flags = IPROC_CLK_AON,
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+ .enable = ENABLE_VAL(0x4, 16, 10, 22),
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+ .mdiv = REG_VAL(0x1c, 8, 8),
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+ },
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+ [BCM_NSP_GENPLL_SATA2_CLK] = {
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+ .channel = BCM_NSP_GENPLL_SATA2_CLK,
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+ .flags = IPROC_CLK_AON,
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+ .enable = ENABLE_VAL(0x4, 17, 11, 23),
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+ .mdiv = REG_VAL(0x1c, 0, 8),
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+ },
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+};
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+
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+static void __init nsp_genpll_clk_init(struct device_node *node)
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+{
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+ iproc_pll_clk_setup(node, &genpll, NULL, 0, genpll_clk,
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+ ARRAY_SIZE(genpll_clk));
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+}
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+CLK_OF_DECLARE(nsp_genpll_clk, "brcm,nsp-genpll", nsp_genpll_clk_init);
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+
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+static const struct iproc_pll_ctrl lcpll0 = {
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+ .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL,
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+ .aon = AON_VAL(0x0, 1, 24, 0),
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+ .reset = RESET_VAL(0x0, 23, 22, 16, 3, 12, 4, 19, 4),
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+ .ndiv_int = REG_VAL(0x4, 20, 8),
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+ .ndiv_frac = REG_VAL(0x4, 0, 20),
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+ .pdiv = REG_VAL(0x4, 28, 3),
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+ .status = REG_VAL(0x10, 12, 1),
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+};
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+
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+static const struct iproc_clk_ctrl lcpll0_clk[] = {
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+ [BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK] = {
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+ .channel = BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK,
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+ .flags = IPROC_CLK_AON,
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+ .enable = ENABLE_VAL(0x0, 6, 3, 9),
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+ .mdiv = REG_VAL(0x8, 24, 8),
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+ },
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+ [BCM_NSP_LCPLL0_SDIO_CLK] = {
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+ .channel = BCM_NSP_LCPLL0_SDIO_CLK,
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+ .flags = IPROC_CLK_AON,
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+ .enable = ENABLE_VAL(0x0, 7, 4, 10),
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+ .mdiv = REG_VAL(0x8, 16, 8),
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+ },
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+ [BCM_NSP_LCPLL0_DDR_PHY_CLK] = {
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+ .channel = BCM_NSP_LCPLL0_DDR_PHY_CLK,
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+ .flags = IPROC_CLK_AON,
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+ .enable = ENABLE_VAL(0x0, 8, 5, 11),
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+ .mdiv = REG_VAL(0x8, 8, 8),
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+ },
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+};
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+
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+static void __init nsp_lcpll0_clk_init(struct device_node *node)
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+{
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+ iproc_pll_clk_setup(node, &lcpll0, NULL, 0, lcpll0_clk,
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+ ARRAY_SIZE(lcpll0_clk));
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+}
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+CLK_OF_DECLARE(nsp_lcpll0_clk, "brcm,nsp-lcpll0", nsp_lcpll0_clk_init);
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--- /dev/null
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+++ b/include/dt-bindings/clock/bcm-nsp.h
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@@ -0,0 +1,51 @@
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+/*
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+ * BSD LICENSE
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+ *
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+ * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
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+ *
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+ * Redistribution and use in source and binary forms, with or without
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+ * modification, are permitted provided that the following conditions
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+ * are met:
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+ *
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+ * * Redistributions of source code must retain the above copyright
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+ * notice, this list of conditions and the following disclaimer.
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+ * * Redistributions in binary form must reproduce the above copyright
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+ * notice, this list of conditions and the following disclaimer in
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+ * the documentation and/or other materials provided with the
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+ * distribution.
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+ * * Neither the name of Broadcom Corporation nor the names of its
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+ * contributors may be used to endorse or promote products derived
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+ * from this software without specific prior written permission.
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+ *
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+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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+ */
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+
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+#ifndef _CLOCK_BCM_NSP_H
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+#define _CLOCK_BCM_NSP_H
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+
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+/* GENPLL clock channel ID */
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+#define BCM_NSP_GENPLL 0
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+#define BCM_NSP_GENPLL_PHY_CLK 1
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+#define BCM_NSP_GENPLL_ENET_SW_CLK 2
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+#define BCM_NSP_GENPLL_USB_PHY_REF_CLK 3
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+#define BCM_NSP_GENPLL_IPROCFAST_CLK 4
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+#define BCM_NSP_GENPLL_SATA1_CLK 5
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+#define BCM_NSP_GENPLL_SATA2_CLK 6
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+
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+/* LCPLL0 clock channel ID */
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+#define BCM_NSP_LCPLL0 0
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+#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK 1
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+#define BCM_NSP_LCPLL0_SDIO_CLK 2
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+#define BCM_NSP_LCPLL0_DDR_PHY_CLK 3
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+
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+#endif /* _CLOCK_BCM_NSP_H */
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