mirror of
git://git.openwrt.org/openwrt/openwrt.git
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d41d9befb9
Add u-boot bootloader based on 2023.01 to support D1-based boards, currently: - Dongshan Nezha STU - LicheePi RV Dock - MangoPi MQ-Pro - Nezha D1 Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
324 lines
12 KiB
Diff
324 lines
12 KiB
Diff
From 4c0c00e7131baf410702555342337c178dd0de98 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Sun, 30 Oct 2022 16:04:47 -0500
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Subject: [PATCH 19/90] sunxi: mmc: Move header to the driver directory
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The MMC controller driver is (and ought to be) the only user of these
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register definitions. Put them in a header next to the driver to remove
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the dependency on a specific ARM platform's headers.
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Due to the sunxi_mmc_init() prototype, the file was not renamed. None of
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the register definitions were changed.
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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arch/arm/include/asm/arch-sunxi/mmc.h | 139 +-------------------------
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drivers/mmc/sunxi_mmc.c | 4 +
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drivers/mmc/sunxi_mmc.h | 138 +++++++++++++++++++++++++
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3 files changed, 146 insertions(+), 135 deletions(-)
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create mode 100644 drivers/mmc/sunxi_mmc.h
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--- a/arch/arm/include/asm/arch-sunxi/mmc.h
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+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
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@@ -1,139 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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-/*
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- * (C) Copyright 2007-2011
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- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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- * Aaron <leafy.myeh@allwinnertech.com>
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- *
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- * MMC register definition for allwinner sunxi platform.
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- */
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-#ifndef _SUNXI_MMC_H
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-#define _SUNXI_MMC_H
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-
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-#include <linux/types.h>
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-
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-struct sunxi_mmc {
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- u32 gctrl; /* 0x00 global control */
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- u32 clkcr; /* 0x04 clock control */
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- u32 timeout; /* 0x08 time out */
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- u32 width; /* 0x0c bus width */
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- u32 blksz; /* 0x10 block size */
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- u32 bytecnt; /* 0x14 byte count */
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- u32 cmd; /* 0x18 command */
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- u32 arg; /* 0x1c argument */
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- u32 resp0; /* 0x20 response 0 */
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- u32 resp1; /* 0x24 response 1 */
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- u32 resp2; /* 0x28 response 2 */
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- u32 resp3; /* 0x2c response 3 */
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- u32 imask; /* 0x30 interrupt mask */
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- u32 mint; /* 0x34 masked interrupt status */
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- u32 rint; /* 0x38 raw interrupt status */
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- u32 status; /* 0x3c status */
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- u32 ftrglevel; /* 0x40 FIFO threshold watermark*/
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- u32 funcsel; /* 0x44 function select */
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- u32 cbcr; /* 0x48 CIU byte count */
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- u32 bbcr; /* 0x4c BIU byte count */
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- u32 dbgc; /* 0x50 debug enable */
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- u32 res0; /* 0x54 reserved */
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- u32 a12a; /* 0x58 Auto command 12 argument */
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- u32 ntsr; /* 0x5c New timing set register */
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- u32 res1[8];
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- u32 dmac; /* 0x80 internal DMA control */
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- u32 dlba; /* 0x84 internal DMA descr list base address */
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- u32 idst; /* 0x88 internal DMA status */
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- u32 idie; /* 0x8c internal DMA interrupt enable */
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- u32 chda; /* 0x90 */
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- u32 cbda; /* 0x94 */
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- u32 res2[26];
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-#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
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- u32 res3[17];
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- u32 samp_dl;
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- u32 res4[46];
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-#endif
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- u32 fifo; /* 0x100 / 0x200 FIFO access address */
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-};
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-
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-#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17)
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-#define SUNXI_MMC_CLK_ENABLE (0x1 << 16)
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-#define SUNXI_MMC_CLK_DIVIDER_MASK (0xff)
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-
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-#define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0)
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-#define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1)
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-#define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2)
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-#define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\
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- SUNXI_MMC_GCTRL_FIFO_RESET|\
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- SUNXI_MMC_GCTRL_DMA_RESET)
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-#define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5)
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-#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31)
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-
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-#define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6)
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-#define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7)
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-#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8)
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-#define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9)
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-#define SUNXI_MMC_CMD_WRITE (0x1 << 10)
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-#define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12)
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-#define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13)
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-#define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15)
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-#define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21)
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-#define SUNXI_MMC_CMD_START (0x1 << 31)
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-
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-#define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1)
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-#define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2)
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-#define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3)
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-#define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4)
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-#define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5)
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-#define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6)
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-#define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7)
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-#define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8)
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-#define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9)
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-#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10)
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-#define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11)
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-#define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12)
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-#define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13)
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-#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14)
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-#define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15)
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-#define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16)
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-#define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30)
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-#define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31)
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-#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \
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- (SUNXI_MMC_RINT_RESP_ERROR | \
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- SUNXI_MMC_RINT_RESP_CRC_ERROR | \
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- SUNXI_MMC_RINT_DATA_CRC_ERROR | \
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- SUNXI_MMC_RINT_RESP_TIMEOUT | \
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- SUNXI_MMC_RINT_DATA_TIMEOUT | \
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- SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \
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- SUNXI_MMC_RINT_FIFO_RUN_ERROR | \
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- SUNXI_MMC_RINT_HARD_WARE_LOCKED | \
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- SUNXI_MMC_RINT_START_BIT_ERROR | \
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- SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */
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-#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \
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- (SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \
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- SUNXI_MMC_RINT_DATA_OVER | \
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- SUNXI_MMC_RINT_COMMAND_DONE | \
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- SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE)
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-
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-#define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0)
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-#define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1)
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-#define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2)
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-#define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3)
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-#define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8)
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-#define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9)
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-#define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10)
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-#define SUNXI_MMC_STATUS_FIFO_LEVEL(reg) (((reg) >> 17) & 0x3fff)
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-
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-#define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31)
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-
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-#define SUNXI_MMC_IDMAC_RESET (0x1 << 0)
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-#define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1)
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-#define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7)
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-
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-#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0)
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-#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1)
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-
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-#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)
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-#define SUNXI_MMC_COMMON_RESET (1 << 18)
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-
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-#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7)
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+#ifndef _ASM_ARCH_MMC_H_
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+#define _ASM_ARCH_MMC_H_
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struct mmc *sunxi_mmc_init(int sdc_no);
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-#endif /* _SUNXI_MMC_H */
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+
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+#endif /* _ASM_ARCH_MMC_H_ */
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--- a/drivers/mmc/sunxi_mmc.c
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+++ b/drivers/mmc/sunxi_mmc.c
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@@ -25,9 +25,13 @@
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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+#if !CONFIG_IS_ENABLED(DM_MMC)
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#include <asm/arch/mmc.h>
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+#endif
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#include <linux/delay.h>
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+#include "sunxi_mmc.h"
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+
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#ifndef CCM_MMC_CTRL_MODE_SEL_NEW
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#define CCM_MMC_CTRL_MODE_SEL_NEW 0
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#endif
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--- /dev/null
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+++ b/drivers/mmc/sunxi_mmc.h
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@@ -0,0 +1,138 @@
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+/* SPDX-License-Identifier: GPL-2.0+ */
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+/*
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+ * (C) Copyright 2007-2011
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+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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+ * Aaron <leafy.myeh@allwinnertech.com>
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+ *
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+ * MMC register definition for allwinner sunxi platform.
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+ */
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+
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+#ifndef _SUNXI_MMC_H
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+#define _SUNXI_MMC_H
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+
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+#include <linux/types.h>
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+
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+struct sunxi_mmc {
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+ u32 gctrl; /* 0x00 global control */
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+ u32 clkcr; /* 0x04 clock control */
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+ u32 timeout; /* 0x08 time out */
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+ u32 width; /* 0x0c bus width */
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+ u32 blksz; /* 0x10 block size */
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+ u32 bytecnt; /* 0x14 byte count */
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+ u32 cmd; /* 0x18 command */
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+ u32 arg; /* 0x1c argument */
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+ u32 resp0; /* 0x20 response 0 */
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+ u32 resp1; /* 0x24 response 1 */
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+ u32 resp2; /* 0x28 response 2 */
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+ u32 resp3; /* 0x2c response 3 */
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+ u32 imask; /* 0x30 interrupt mask */
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+ u32 mint; /* 0x34 masked interrupt status */
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+ u32 rint; /* 0x38 raw interrupt status */
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+ u32 status; /* 0x3c status */
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+ u32 ftrglevel; /* 0x40 FIFO threshold watermark*/
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+ u32 funcsel; /* 0x44 function select */
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+ u32 cbcr; /* 0x48 CIU byte count */
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+ u32 bbcr; /* 0x4c BIU byte count */
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+ u32 dbgc; /* 0x50 debug enable */
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+ u32 res0; /* 0x54 reserved */
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+ u32 a12a; /* 0x58 Auto command 12 argument */
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+ u32 ntsr; /* 0x5c New timing set register */
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+ u32 res1[8];
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+ u32 dmac; /* 0x80 internal DMA control */
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+ u32 dlba; /* 0x84 internal DMA descr list base address */
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+ u32 idst; /* 0x88 internal DMA status */
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+ u32 idie; /* 0x8c internal DMA interrupt enable */
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+ u32 chda; /* 0x90 */
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+ u32 cbda; /* 0x94 */
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+ u32 res2[26];
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+#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
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+ u32 res3[17];
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+ u32 samp_dl;
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+ u32 res4[46];
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+#endif
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+ u32 fifo; /* 0x100 / 0x200 FIFO access address */
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+};
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+
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+#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17)
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+#define SUNXI_MMC_CLK_ENABLE (0x1 << 16)
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+#define SUNXI_MMC_CLK_DIVIDER_MASK (0xff)
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+
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+#define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0)
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+#define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1)
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+#define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2)
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+#define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\
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+ SUNXI_MMC_GCTRL_FIFO_RESET|\
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+ SUNXI_MMC_GCTRL_DMA_RESET)
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+#define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5)
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+#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31)
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+
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+#define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6)
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+#define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7)
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+#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8)
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+#define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9)
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+#define SUNXI_MMC_CMD_WRITE (0x1 << 10)
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+#define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12)
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+#define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13)
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+#define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15)
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+#define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21)
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+#define SUNXI_MMC_CMD_START (0x1 << 31)
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+
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+#define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1)
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+#define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2)
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+#define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3)
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+#define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4)
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+#define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5)
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+#define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6)
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+#define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7)
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+#define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8)
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+#define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9)
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+#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10)
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+#define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11)
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+#define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12)
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+#define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13)
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+#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14)
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+#define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15)
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+#define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16)
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+#define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30)
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+#define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31)
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+#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \
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+ (SUNXI_MMC_RINT_RESP_ERROR | \
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+ SUNXI_MMC_RINT_RESP_CRC_ERROR | \
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+ SUNXI_MMC_RINT_DATA_CRC_ERROR | \
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+ SUNXI_MMC_RINT_RESP_TIMEOUT | \
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+ SUNXI_MMC_RINT_DATA_TIMEOUT | \
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+ SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \
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+ SUNXI_MMC_RINT_FIFO_RUN_ERROR | \
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+ SUNXI_MMC_RINT_HARD_WARE_LOCKED | \
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+ SUNXI_MMC_RINT_START_BIT_ERROR | \
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+ SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */
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+#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \
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+ (SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \
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+ SUNXI_MMC_RINT_DATA_OVER | \
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+ SUNXI_MMC_RINT_COMMAND_DONE | \
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+ SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE)
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+
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+#define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0)
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+#define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1)
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+#define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2)
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+#define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3)
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+#define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8)
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+#define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9)
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+#define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10)
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+#define SUNXI_MMC_STATUS_FIFO_LEVEL(reg) (((reg) >> 17) & 0x3fff)
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+
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+#define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31)
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+
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+#define SUNXI_MMC_IDMAC_RESET (0x1 << 0)
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+#define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1)
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+#define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7)
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+
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+#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0)
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+#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1)
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+
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+#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)
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+#define SUNXI_MMC_COMMON_RESET (1 << 18)
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+
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+#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7)
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+
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+#endif /* _SUNXI_MMC_H */
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