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a1043fda8b
Currently phy packages (like RTL8214x/RTL8218x) are patched and initialized as soon as the first phy of the package is found. In this situation the shared structure is not finalized because devm_phy_package_join() has only been called for the first phy. This is no issue as the patching directly hammers the bus addresses for the follow-up phys. In the future we want to simplify the package handling and allow to access all phy_device structures from only one phy_device of the package. With this we can use normal phy_read/phy_write. Switch the probing logic to "late patching". With this we will initialize the firmware of the package when the last phy of the package has been found and thus the shared structure is complete. Provide get_base_phy() as the first package helper that allows to determine the first phy of the package from any other phy. While we are here drop the shared structure that only repeats the phy name and has no other use. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: https://github.com/openwrt/openwrt/pull/19810 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
83 lines
2.8 KiB
C
83 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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struct __attribute__ ((__packed__)) part {
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uint16_t start;
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uint8_t wordsize;
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uint8_t words;
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};
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struct __attribute__ ((__packed__)) fw_header {
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uint32_t magic;
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uint32_t phy;
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uint32_t checksum;
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uint32_t version;
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struct part parts[10];
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};
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/* TODO: fixed path? */
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#define FIRMWARE_838X_8380_1 "rtl838x_phy/rtl838x_8380.fw"
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#define FIRMWARE_838X_8214FC_1 "rtl838x_phy/rtl838x_8214fc.fw"
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#define FIRMWARE_838X_8218b_1 "rtl838x_phy/rtl838x_8218b.fw"
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#define PHY_ID_RTL8214C 0x001cc942
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#define PHY_ID_RTL8218B_E 0x001cc980
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#define PHY_ID_RTL8214_OR_8218 0x001cc981
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#define PHY_ID_RTL8218D 0x001cc983
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#define PHY_ID_RTL8218B_I 0x001cca40
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#define PHY_ID_RTL8221B 0x001cc849
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#define PHY_ID_RTL8226 0x001cc838
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#define PHY_ID_RTL8390_GENERIC 0x001ccab0
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#define PHY_ID_RTL8393_I 0x001c8393
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#define PHY_ID_RTL9300_I 0x338002a0
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/* These PHYs share the same id (0x001cc981) */
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#define PHY_IS_NOT_RTL821X 0
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#define PHY_IS_RTL8214FC 1
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#define PHY_IS_RTL8214FB 2
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#define PHY_IS_RTL8218B_E 3
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/* Registers of the internal Serdes of the 8380 */
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#define RTL838X_SDS_MODE_SEL (0x0028)
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#define RTL838X_SDS_CFG_REG (0x0034)
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#define RTL838X_INT_MODE_CTRL (0x005c)
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#define RTL838X_DMY_REG31 (0x3b28)
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#define RTL8380_SDS4_FIB_REG0 (0xF800)
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#define RTL838X_SDS4_REG28 (0xef80)
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#define RTL838X_SDS4_DUMMY0 (0xef8c)
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#define RTL838X_SDS5_EXT_REG6 (0xf18c)
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#define RTL838X_SDS4_FIB_REG0 (RTL838X_SDS4_REG28 + 0x880)
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#define RTL838X_SDS5_FIB_REG0 (RTL838X_SDS4_REG28 + 0x980)
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/* Registers of the internal SerDes of the RTL8390 */
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#define RTL839X_SDS12_13_XSG0 (0xB800)
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/* Registers of the internal Serdes of the 9300 */
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#define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C)
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/* Registers of the internal SerDes of the 9310 */
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#define RTL931X_SERDES_MODE_CTRL (0x13cc)
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#define RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR (0x13F4)
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#define RTL931X_MAC_SERDES_MODE_CTRL(sds) (0x136C + (((sds) << 2)))
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int rtl9300_serdes_setup(int port, int sds_num, phy_interface_t phy_mode);
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int rtl931x_sds_cmu_band_get(int sds, phy_interface_t mode);
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void rtl931x_sds_init(u32 sds, phy_interface_t mode);
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/*
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* TODO: The following functions are currently not in use. So compiler will complain if
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* they are static and not made available externally. Collect them in this section to
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* preserve for future use.
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*/
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void rtl9300_do_rx_calibration_3(int sds_num, phy_interface_t phy_mode);
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int rtl9300_sds_clock_wait(int timeout);
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int rtl9300_sds_cmu_band_get(int sds);
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void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[]);
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void rtl9300_sds_rxcal_dcvs_manual(u32 sds_num, u32 dcvs_id, bool manual, u32 dvcs_list[]);
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void rtl9300_sds_set(int sds_num, u32 mode);
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int rtl931x_link_sts_get(u32 sds);
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void rtl931x_sds_fiber_disable(u32 sds);
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int rtl931x_sds_cmu_band_set(int sds, bool enable, u32 band, phy_interface_t mode); |