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95bd7a76a1
Update the ipq9574 PCS driver the version provided by Qualcomm via github. The updated driver simplifies link up handling by removing unnecessary clock rate changes. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Link: https://github.com/openwrt/openwrt/pull/20993 Signed-off-by: Robert Marko <robimarko@gmail.com>
140 lines
3.7 KiB
Diff
140 lines
3.7 KiB
Diff
From d6f184181b076cbb54f152994f5bc73ce524a67e Mon Sep 17 00:00:00 2001
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From: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Date: Sun, 11 May 2025 18:21:00 -0500
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Subject: [PATCH] arm64: dts: qcom: ipq9574: add PCS uniphy nodes
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IPQ9574 has three uniphy blocks. IPQ9554 lacks uniphy1. They take
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their system and AHB clocks from NSSCC, and also feed NSSCC with
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the clocks that are intended for the PHYs. This is not a cirular
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dependency. Add nodes for these uniphy blocks, and the clocks they
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feed back to the NSSCC node.
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Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq9574.dtsi | 100 ++++++++++++++++++++++++--
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1 file changed, 94 insertions(+), 6 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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@@ -9,6 +9,7 @@
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#include <dt-bindings/clock/qcom,apss-ipq.h>
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#include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
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#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
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+#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
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#include <dt-bindings/interconnect/qcom,ipq9574.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
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@@ -1247,12 +1248,12 @@
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<&cmn_pll NSS_1200MHZ_CLK>,
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<&cmn_pll PPE_353MHZ_CLK>,
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<&gcc GPLL0_OUT_AUX>,
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- <0>,
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- <0>,
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- <0>,
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- <0>,
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- <0>,
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- <0>,
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+ <&pcs0 0>,
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+ <&pcs0 1>,
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+ <&pcs1 0>,
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+ <&pcs1 1>,
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+ <&pcs2 0>,
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+ <&pcs2 1>,
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<&gcc GCC_NSSCC_CLK>;
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clock-names = "xo",
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"nss_1200",
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@@ -1269,6 +1270,93 @@
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#reset-cells = <1>;
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#interconnect-cells = <1>;
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};
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+
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+ pcs0: ethernet-pcs@7a00000 {
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+ compatible = "qcom,ipq9574-pcs";
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+ reg = <0x7a00000 0x10000>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ clocks = <&gcc GCC_UNIPHY0_SYS_CLK>,
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+ <&gcc GCC_UNIPHY0_AHB_CLK>;
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+ clock-names = "sys",
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+ "ahb";
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+ resets = <&gcc GCC_UNIPHY0_XPCS_RESET>;
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+ #clock-cells = <1>;
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+
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+ pcs0_ch0: pcs-mii@0 {
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+ reg = <0>;
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+ clocks = <&nsscc NSS_CC_UNIPHY_PORT1_RX_CLK>,
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+ <&nsscc NSS_CC_UNIPHY_PORT1_TX_CLK>;
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+ clock-names = "rx",
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+ "tx";
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+ };
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+
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+ pcs0_ch1: pcs-mii@1 {
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+ reg = <1>;
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+ clocks = <&nsscc NSS_CC_UNIPHY_PORT2_RX_CLK>,
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+ <&nsscc NSS_CC_UNIPHY_PORT2_TX_CLK>;
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+ clock-names = "rx",
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+ "tx";
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+ };
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+
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+ pcs0_ch2: pcs-mii@2 {
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+ reg = <2>;
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+ clocks = <&nsscc NSS_CC_UNIPHY_PORT3_RX_CLK>,
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+ <&nsscc NSS_CC_UNIPHY_PORT3_TX_CLK>;
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+ clock-names = "rx",
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+ "tx";
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+ };
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+
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+ pcs0_ch3: pcs-mii@3 {
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+ reg = <3>;
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+ clocks = <&nsscc NSS_CC_UNIPHY_PORT4_RX_CLK>,
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+ <&nsscc NSS_CC_UNIPHY_PORT4_TX_CLK>;
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+ clock-names = "rx",
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+ "tx";
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+ };
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+ };
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+
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+ pcs1: ethernet-pcs@7a10000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "qcom,ipq9574-pcs";
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+ reg = <0x7a10000 0x10000>;
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+ clocks = <&gcc GCC_UNIPHY1_SYS_CLK>,
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+ <&gcc GCC_UNIPHY1_AHB_CLK>;
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+ clock-names = "sys",
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+ "ahb";
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+ resets = <&gcc GCC_UNIPHY1_XPCS_RESET>;
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+ #clock-cells = <1>;
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+
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+ pcs1_ch0: pcs-mii@0 {
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+ reg = <0>;
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+ clocks = <&nsscc NSS_CC_UNIPHY_PORT5_RX_CLK>,
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+ <&nsscc NSS_CC_UNIPHY_PORT5_TX_CLK>;
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+ clock-names = "rx",
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+ "tx";
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+ };
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+ };
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+
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+ pcs2: ethernet-pcs@7a20000 {
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+ compatible = "qcom,ipq9574-pcs";
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+ reg = <0x7a20000 0x10000>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ clocks = <&gcc GCC_UNIPHY2_SYS_CLK>,
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+ <&gcc GCC_UNIPHY2_AHB_CLK>;
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+ clock-names = "sys",
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+ "ahb";
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+ resets = <&gcc GCC_UNIPHY2_XPCS_RESET>;
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+ #clock-cells = <1>;
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+
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+ pcs2_ch0: pcs-mii@0 {
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+ reg = <0>;
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+ clocks = <&nsscc NSS_CC_UNIPHY_PORT6_RX_CLK>,
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+ <&nsscc NSS_CC_UNIPHY_PORT6_TX_CLK>;
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+ clock-names = "rx",
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+ "tx";
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+ };
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+ };
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};
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thermal-zones {
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