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623180a422
RTL93XX reached the point where the SerDes' are no longer treated as regular PHYs. Instead, they are managed by the dedicated PCS driver. Thus, all device tree definitions should follow this change. Remove the pseudo-PHYs for the SerDes (so far usually defined with macro INTERNAL_PHY) and corresponding 'phy-handle's from all SFP ports. This removes a long-lasting confusion from our Realtek driver(s). Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com> Link: https://github.com/openwrt/openwrt/pull/20577 Signed-off-by: Robert Marko <robimarko@gmail.com>
603 lines
12 KiB
Plaintext
603 lines
12 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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#include "rtl931x.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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/ {
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chosen {
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/* get active mtdparts from u-boot */
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/delete-property/ bootargs;
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};
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aliases {
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led-boot = &led_status;
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led-running = &led_status;
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led-failsafe = &led_status;
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led-upgrade = &led_status;
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label-mac-device = ðernet0;
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};
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memory@0 {
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reg = <0x00000000 0x10000000>, /* low mem 256 MiB */
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<0x90000000 0x10000000>; /* high mem 256 MiB */
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};
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gpio-restart {
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compatible = "gpio-restart";
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gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
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};
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keys {
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compatible = "gpio-keys-polled";
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poll-interval = <20>;
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mode {
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label = "reset";
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gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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sfp0: sfp-lan25 {
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compatible = "sff,sfp";
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_disable_spi0>;
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i2c-bus = <&i2c0>;
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los-gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 9 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>;
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};
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sfp1: sfp-lan26 {
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compatible = "sff,sfp";
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_disable_spi0_cs0>,
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<&pinmux_disable_spi0_cs1>;
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i2c-bus = <&i2c1>;
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los-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 12 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
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};
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sfp2: sfp-lan27 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c2>;
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los-gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 22 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio0 23 GPIO_ACTIVE_HIGH>;
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};
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sfp3: sfp-lan28 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c3>;
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los-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_disable_sys_led>;
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led_status: led-0 {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_STATUS;
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gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
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};
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led-1 {
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_ALARM;
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gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
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};
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};
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led_set@0 {
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compatible = "realtek,rtl9300-leds";
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active-low;
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led_set0 = <(RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_LINK |
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RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_1G | RTL93XX_LED_SET_100M |
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RTL93XX_LED_SET_10M | RTL93XX_LED_SET_LINK |
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RTL93XX_LED_SET_ACT)>;
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led_set1 = <(RTL93XX_LED_SET_1G | RTL93XX_LED_SET_LINK |
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RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_LINK |
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RTL93XX_LED_SET_ACT)>;
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};
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};
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&i2c_mst1 {
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status = "okay";
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/* i2c of the SFP+ cage on port 24 */
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i2c0: i2c@0 {
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reg = <0>;
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};
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/* i2c of the SFP+ cage on port 25 */
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i2c1: i2c@1 {
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reg = <1>;
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};
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/* i2c of the SFP+ cage on port 26 */
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i2c2: i2c@2 {
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reg = <2>;
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};
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/* i2c of the SFP+ cage on port 27 */
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i2c3: i2c@3 {
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reg = <3>;
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};
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/* i2c of adt7476 hwmonitor */
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i2c@4 {
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reg = <4>;
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adt7476@2e {
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compatible = "adi,adt7476";
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reg = <0x2e>;
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};
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};
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};
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&mdio_aux {
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status = "okay";
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gpio1: expander@24 {
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compatible = "realtek,rtl8231";
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reg = <24>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&gpio1 0 0 37>;
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led-controller {
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compatible = "realtek,rtl8231-leds";
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status = "disabled";
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};
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0xc0000>;
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read-only;
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};
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partition@c0000 {
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label = "u-boot-env";
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reg = <0xc0000 0x10000>;
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nvmem-layout {
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compatible = "u-boot,env";
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macaddr_ubootenv_ethaddr: ethaddr {
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#nvmem-cell-cells = <1>;
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};
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};
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};
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partition@d0000 {
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label = "u-boot-env2";
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reg = <0xd0000 0x10000>;
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};
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partition@e0000 {
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label = "reserved";
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reg = <0xe0000 0x500000>;
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};
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partition@5e0000 {
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label = "firmware1";
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reg = <0x5e0000 0xd10000>;
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compatible = "openwrt,uimage", "denx,uimage";
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openwrt,ih-magic = <0x93100000>;
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};
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partition@12f0000 {
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label = "firmware2";
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reg = <0x12f0000 0xd10000>;
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compatible = "openwrt,uimage", "denx,uimage";
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openwrt,ih-magic = <0x93100000>;
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};
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};
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};
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};
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ðernet0 {
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nvmem-cells = <&macaddr_ubootenv_ethaddr 0>;
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nvmem-cell-names = "mac-address";
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};
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&mdio_ctrl {
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_enable_mdc_mdio_0>,
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<&pinmux_enable_mdc_mdio_1>;
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};
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&mdio_bus0 {
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/* External RTL8224 PHY */
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phy0: ethernet-phy@0 {
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reg = <0>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <0 0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <0 1>;
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};
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phy4: ethernet-phy@4 {
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reg = <4>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <0 2>;
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};
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phy5: ethernet-phy@5 {
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reg = <5>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <0 3>;
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};
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phy8: ethernet-phy@8 {
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reg = <8>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <0 4>;
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};
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phy9: ethernet-phy@9 {
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reg = <9>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <0 5>;
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};
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phy12: ethernet-phy@12 {
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reg = <12>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <0 6>;
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};
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phy13: ethernet-phy@13 {
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reg = <13>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <0 7>;
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};
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phy16: ethernet-phy@16 {
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reg = <16>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <0 8>;
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};
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phy17: ethernet-phy@17 {
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reg = <17>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <0 9>;
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};
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phy20: ethernet-phy@20 {
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reg = <20>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <0 10>;
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};
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phy21: ethernet-phy@21 {
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reg = <21>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <0 11>;
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};
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phy24: ethernet-phy@24 {
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reg = <24>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <1 12>;
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};
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phy25: ethernet-phy@25 {
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reg = <25>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <1 13>;
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};
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phy28: ethernet-phy@28 {
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reg = <28>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <1 14>;
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};
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phy29: ethernet-phy@29 {
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reg = <29>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <1 15>;
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};
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phy32: ethernet-phy@32 {
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reg = <32>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <1 16>;
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};
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phy33: ethernet-phy@33 {
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reg = <33>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <1 17>;
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};
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phy36: ethernet-phy@36 {
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reg = <36>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <1 18>;
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};
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phy37: ethernet-phy@37 {
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reg = <37>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <1 19>;
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};
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phy40: ethernet-phy@40 {
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reg = <40>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <1 20>;
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};
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phy41: ethernet-phy@41 {
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reg = <41>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <1 21>;
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};
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phy44: ethernet-phy@44 {
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reg = <44>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <1 22>;
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};
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phy45: ethernet-phy@45 {
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reg = <45>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <1 23>;
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};
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};
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&switch0 {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* copper ethernet */
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SWITCH_PORT_SDS(0, 1, 2, 10g-qxgmii)
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SWITCH_PORT_SDS(1, 2, 2, 10g-qxgmii)
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SWITCH_PORT_SDS(4, 3, 2, 10g-qxgmii)
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SWITCH_PORT_SDS(5, 4, 2, 10g-qxgmii)
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SWITCH_PORT_SDS(8, 5, 3, 10g-qxgmii)
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SWITCH_PORT_SDS(9, 6, 3, 10g-qxgmii)
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SWITCH_PORT_SDS(12, 7, 3, 10g-qxgmii)
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SWITCH_PORT_SDS(13, 8, 3, 10g-qxgmii)
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SWITCH_PORT_SDS(16, 9, 4, 10g-qxgmii)
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SWITCH_PORT_SDS(17, 10, 4, 10g-qxgmii)
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SWITCH_PORT_SDS(20, 11, 4, 10g-qxgmii)
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SWITCH_PORT_SDS(21, 12, 4, 10g-qxgmii)
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SWITCH_PORT_SDS(24, 13, 5, 10g-qxgmii)
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SWITCH_PORT_SDS(25, 14, 5, 10g-qxgmii)
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SWITCH_PORT_SDS(28, 15, 5, 10g-qxgmii)
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SWITCH_PORT_SDS(29, 16, 5, 10g-qxgmii)
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SWITCH_PORT_SDS(32, 17, 6, 10g-qxgmii)
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SWITCH_PORT_SDS(33, 18, 6, 10g-qxgmii)
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SWITCH_PORT_SDS(36, 19, 6, 10g-qxgmii)
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SWITCH_PORT_SDS(37, 20, 6, 10g-qxgmii)
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SWITCH_PORT_SDS(40, 21, 7, 10g-qxgmii)
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SWITCH_PORT_SDS(41, 22, 7, 10g-qxgmii)
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SWITCH_PORT_SDS(44, 23, 7, 10g-qxgmii)
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SWITCH_PORT_SDS(45, 24, 7, 10g-qxgmii)
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port@48 {
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reg = <48>;
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label = "lan25";
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pcs-handle = <&serdes8>;
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phy-mode = "1000base-x";
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sfp = <&sfp0>;
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led-set = <1>;
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managed = "in-band-status";
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nvmem-cells = <&macaddr_ubootenv_ethaddr 25>;
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nvmem-cell-names = "mac-address";
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};
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port@50 {
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reg = <50>;
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label = "lan26";
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pcs-handle = <&serdes9>;
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phy-mode = "1000base-x";
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sfp = <&sfp1>;
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led-set = <1>;
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managed = "in-band-status";
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nvmem-cells = <&macaddr_ubootenv_ethaddr 26>;
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nvmem-cell-names = "mac-address";
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};
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port@52 {
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reg = <52>;
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label = "lan27";
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pcs-handle = <&serdes10>;
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phy-mode = "1000base-x";
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sfp = <&sfp2>;
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led-set = <1>;
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managed = "in-band-status";
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nvmem-cells = <&macaddr_ubootenv_ethaddr 27>;
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nvmem-cell-names = "mac-address";
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};
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port@53 {
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reg = <53>;
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label = "lan28";
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pcs-handle = <&serdes11>;
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phy-mode = "1000base-x";
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sfp = <&sfp3>;
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led-set = <1>;
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managed = "in-band-status";
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nvmem-cells = <&macaddr_ubootenv_ethaddr 28>;
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nvmem-cell-names = "mac-address";
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};
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/* cpu */
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port@56 {
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ethernet = <ðernet0>;
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reg = <56>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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&port0 {
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nvmem-cells = <&macaddr_ubootenv_ethaddr 1>;
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nvmem-cell-names = "mac-address";
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};
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&port1 {
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nvmem-cells = <&macaddr_ubootenv_ethaddr 2>;
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nvmem-cell-names = "mac-address";
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};
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&port4 {
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nvmem-cells = <&macaddr_ubootenv_ethaddr 3>;
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nvmem-cell-names = "mac-address";
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};
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&port5 {
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nvmem-cells = <&macaddr_ubootenv_ethaddr 4>;
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nvmem-cell-names = "mac-address";
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};
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&port8 {
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nvmem-cells = <&macaddr_ubootenv_ethaddr 5>;
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nvmem-cell-names = "mac-address";
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};
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&port9 {
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nvmem-cells = <&macaddr_ubootenv_ethaddr 6>;
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nvmem-cell-names = "mac-address";
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};
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&port12 {
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|
nvmem-cells = <&macaddr_ubootenv_ethaddr 7>;
|
|
nvmem-cell-names = "mac-address";
|
|
};
|
|
|
|
&port13 {
|
|
nvmem-cells = <&macaddr_ubootenv_ethaddr 8>;
|
|
nvmem-cell-names = "mac-address";
|
|
};
|
|
|
|
&port16 {
|
|
nvmem-cells = <&macaddr_ubootenv_ethaddr 9>;
|
|
nvmem-cell-names = "mac-address";
|
|
};
|
|
|
|
&port17 {
|
|
nvmem-cells = <&macaddr_ubootenv_ethaddr 10>;
|
|
nvmem-cell-names = "mac-address";
|
|
};
|
|
|
|
&port20 {
|
|
nvmem-cells = <&macaddr_ubootenv_ethaddr 11>;
|
|
nvmem-cell-names = "mac-address";
|
|
};
|
|
|
|
&port21 {
|
|
nvmem-cells = <&macaddr_ubootenv_ethaddr 12>;
|
|
nvmem-cell-names = "mac-address";
|
|
};
|
|
|
|
&port24 {
|
|
nvmem-cells = <&macaddr_ubootenv_ethaddr 13>;
|
|
nvmem-cell-names = "mac-address";
|
|
};
|
|
|
|
&port25 {
|
|
nvmem-cells = <&macaddr_ubootenv_ethaddr 14>;
|
|
nvmem-cell-names = "mac-address";
|
|
};
|
|
|
|
&port28 {
|
|
nvmem-cells = <&macaddr_ubootenv_ethaddr 15>;
|
|
nvmem-cell-names = "mac-address";
|
|
};
|
|
|
|
&port29 {
|
|
nvmem-cells = <&macaddr_ubootenv_ethaddr 16>;
|
|
nvmem-cell-names = "mac-address";
|
|
};
|
|
|
|
&port32 {
|
|
nvmem-cells = <&macaddr_ubootenv_ethaddr 17>;
|
|
nvmem-cell-names = "mac-address";
|
|
};
|
|
|
|
&port33 {
|
|
nvmem-cells = <&macaddr_ubootenv_ethaddr 18>;
|
|
nvmem-cell-names = "mac-address";
|
|
};
|
|
|
|
&port36 {
|
|
nvmem-cells = <&macaddr_ubootenv_ethaddr 19>;
|
|
nvmem-cell-names = "mac-address";
|
|
};
|
|
|
|
&port37 {
|
|
nvmem-cells = <&macaddr_ubootenv_ethaddr 20>;
|
|
nvmem-cell-names = "mac-address";
|
|
};
|
|
|
|
&port40 {
|
|
nvmem-cells = <&macaddr_ubootenv_ethaddr 21>;
|
|
nvmem-cell-names = "mac-address";
|
|
};
|
|
|
|
&port41 {
|
|
nvmem-cells = <&macaddr_ubootenv_ethaddr 22>;
|
|
nvmem-cell-names = "mac-address";
|
|
};
|
|
|
|
&port44 {
|
|
nvmem-cells = <&macaddr_ubootenv_ethaddr 23>;
|
|
nvmem-cell-names = "mac-address";
|
|
};
|
|
|
|
&port45 {
|
|
nvmem-cells = <&macaddr_ubootenv_ethaddr 24>;
|
|
nvmem-cell-names = "mac-address";
|
|
};
|