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60d2620253
This allows building bcm47xxsflash on ARM. Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
53 lines
1.8 KiB
Diff
53 lines
1.8 KiB
Diff
--- a/drivers/bcma/Kconfig
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+++ b/drivers/bcma/Kconfig
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@@ -76,9 +76,16 @@ config BCMA_PFLASH
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default y
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config BCMA_SFLASH
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- bool
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- depends on BCMA_DRIVER_MIPS
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+ bool "ChipCommon-attached serial flash support"
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+ depends on BCMA_HOST_SOC
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default y
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+ help
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+ Some cheap devices have serial flash connected to the ChipCommon
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+ instead of independent SPI controller. It requires using a separated
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+ driver that implements ChipCommon specific interface communication.
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+
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+ Enabling this symbol will let bcma recognize serial flash and register
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+ it as platform device.
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config BCMA_NFLASH
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bool
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--- a/drivers/bcma/driver_chipcommon_b.c
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+++ b/drivers/bcma/driver_chipcommon_b.c
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@@ -33,11 +33,12 @@ static bool bcma_wait_reg(struct bcma_bu
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void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value)
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{
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struct bcma_bus *bus = ccb->core->bus;
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+ void __iomem *mii = ccb->mii;
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- writel(offset, ccb->mii + 0x00);
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- bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
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- writel(value, ccb->mii + 0x04);
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- bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
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+ writel(offset, mii + BCMA_CCB_MII_MNG_CTL);
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+ bcma_wait_reg(bus, mii + BCMA_CCB_MII_MNG_CTL, 0x0100, 0x0000, 100);
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+ writel(value, mii + BCMA_CCB_MII_MNG_CMD_DATA);
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+ bcma_wait_reg(bus, mii + BCMA_CCB_MII_MNG_CTL, 0x0100, 0x0000, 100);
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}
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EXPORT_SYMBOL_GPL(bcma_chipco_b_mii_write);
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--- a/include/linux/bcma/bcma_driver_chipcommon.h
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+++ b/include/linux/bcma/bcma_driver_chipcommon.h
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@@ -504,6 +504,9 @@
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#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
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#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
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+#define BCMA_CCB_MII_MNG_CTL 0x0000
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+#define BCMA_CCB_MII_MNG_CMD_DATA 0x0004
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+
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/* BCM4331 ChipControl numbers. */
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#define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
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#define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
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