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88a404a2d1
Add a new microchipsw target aimed add supporting Microchip switch SoC-s. Start by supporting LAN969x SoC-s as the first subtarget. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
59 lines
1.8 KiB
Diff
59 lines
1.8 KiB
Diff
From ea6e579557cf85f3b0ed3c94c3e4d69afbcba46c Mon Sep 17 00:00:00 2001
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From: Varshini Rajendran <varshini.rajendran@microchip.com>
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Date: Mon, 8 Sep 2025 09:44:19 +0530
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Subject: [PATCH 110/112] spi: atmel-quadspi: add support for SAM9X7 QSPI
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controller
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Add support for the QuadSPI controller found on the SAM9X7 SoC.
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This controller does not implement pad calibration. It supports
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operation up to 100 MHz, and requires the GCK to run at twice
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the data rate.
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Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
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Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com>
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Link: https://patch.msgid.link/20250908-microchip-qspi-v2-4-8f3d69fdd5c9@microchip.com
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Signed-off-by: Mark Brown <broonie@kernel.org>
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---
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drivers/spi/atmel-quadspi.c | 15 +++++++++++++++
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1 file changed, 15 insertions(+)
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--- a/drivers/spi/atmel-quadspi.c
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+++ b/drivers/spi/atmel-quadspi.c
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@@ -63,6 +63,7 @@
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#define SAMA7G5_QSPI0_MAX_SPEED_HZ 200000000
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#define SAMA7G5_QSPI1_SDR_MAX_SPEED_HZ 133000000
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+#define SAM9X7_QSPI_MAX_SPEED_HZ 100000000
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/* Bitfields in QSPI_CR (Control Register) */
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#define QSPI_CR_QSPIEN BIT(0)
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@@ -1604,6 +1605,16 @@ static const struct atmel_qspi_caps atme
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.has_ricr = true,
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};
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+static const struct atmel_qspi_caps atmel_sam9x7_ospi_caps = {
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+ .max_speed_hz = SAM9X7_QSPI_MAX_SPEED_HZ,
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+ .has_gclk = true,
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+ .octal = true,
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+ .has_dma = true,
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+ .has_2xgclk = true,
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+ .has_padcalib = false,
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+ .has_dllon = false,
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+};
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+
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static const struct atmel_qspi_caps atmel_sama7g5_ospi_caps = {
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.max_speed_hz = SAMA7G5_QSPI0_MAX_SPEED_HZ,
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.has_gclk = true,
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@@ -1637,6 +1648,10 @@ static const struct of_device_id atmel_q
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.compatible = "microchip,sama7g5-qspi",
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.data = &atmel_sama7g5_qspi_caps,
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},
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+ {
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+ .compatible = "microchip,sam9x7-ospi",
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+ .data = &atmel_sam9x7_ospi_caps,
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+ },
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{ /* sentinel */ }
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};
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