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88a404a2d1
Add a new microchipsw target aimed add supporting Microchip switch SoC-s. Start by supporting LAN969x SoC-s as the first subtarget. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
89 lines
3.2 KiB
Diff
89 lines
3.2 KiB
Diff
From e263a2c741eef417e769075e11d32318b8b2b8ab Mon Sep 17 00:00:00 2001
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From: Daniel Machon <daniel.machon@microchip.com>
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Date: Fri, 4 Oct 2024 15:19:31 +0200
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Subject: [PATCH 33/82] net: sparx5: add constants to match data
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Add new struct sparx5_consts, containing all the chip constants that are
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known to be different for Sparx5 and lan969x.
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Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
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Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
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Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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---
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.../ethernet/microchip/sparx5/sparx5_main.c | 21 +++++++++++++++++++
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.../ethernet/microchip/sparx5/sparx5_main.h | 21 +++++++++++++++++++
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2 files changed, 42 insertions(+)
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--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
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+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
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@@ -952,11 +952,32 @@ static const struct sparx5_regs sparx5_r
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.fsize = sparx5_fsize,
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};
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+static const struct sparx5_consts sparx5_consts = {
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+ .n_ports = 65,
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+ .n_ports_all = 70,
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+ .n_hsch_l1_elems = 64,
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+ .n_hsch_queues = 8,
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+ .n_lb_groups = 10,
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+ .n_pgids = 2113, /* (2048 + n_ports) */
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+ .n_sio_clks = 3,
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+ .n_own_upsids = 3,
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+ .n_auto_cals = 7,
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+ .n_filters = 1024,
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+ .n_gates = 1024,
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+ .n_sdlbs = 4096,
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+ .n_dsm_cal_taxis = 8,
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+ .buf_size = 4194280,
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+ .qres_max_prio_idx = 630,
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+ .qres_max_colour_idx = 638,
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+ .tod_pin = 4,
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+};
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+
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static const struct sparx5_match_data sparx5_desc = {
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.iomap = sparx5_main_iomap,
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.iomap_size = ARRAY_SIZE(sparx5_main_iomap),
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.ioranges = 3,
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.regs = &sparx5_regs,
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+ .consts = &sparx5_consts,
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};
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static const struct of_device_id mchp_sparx5_match[] = {
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--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h
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+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h
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@@ -238,6 +238,26 @@ struct sparx5_regs {
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const unsigned int *fsize;
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};
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+struct sparx5_consts {
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+ u32 n_ports; /* Number of front ports */
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+ u32 n_ports_all; /* Number of front ports + internal ports */
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+ u32 n_hsch_l1_elems; /* Number of HSCH layer 1 elements */
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+ u32 n_hsch_queues; /* Number of HSCH queues */
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+ u32 n_lb_groups; /* Number of leacky bucket groupd */
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+ u32 n_pgids; /* Number of PGID's */
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+ u32 n_sio_clks; /* Number of serial IO clocks */
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+ u32 n_own_upsids; /* Number of own UPSID's */
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+ u32 n_auto_cals; /* Number of auto calendars */
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+ u32 n_filters; /* Number of PSFP filters */
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+ u32 n_gates; /* Number of PSFP gates */
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+ u32 n_sdlbs; /* Number of service dual leaky buckets */
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+ u32 n_dsm_cal_taxis; /* Number of DSM calendar taxis */
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+ u32 buf_size; /* Amount of QLIM watermark memory */
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+ u32 qres_max_prio_idx; /* Maximum QRES prio index */
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+ u32 qres_max_colour_idx; /* Maximum QRES colour index */
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+ u32 tod_pin; /* PTP TOD pin */
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+};
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+
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struct sparx5_main_io_resource {
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enum sparx5_target id;
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phys_addr_t offset;
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@@ -246,6 +266,7 @@ struct sparx5_main_io_resource {
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struct sparx5_match_data {
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const struct sparx5_regs *regs;
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+ const struct sparx5_consts *consts;
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const struct sparx5_main_io_resource *iomap;
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int ioranges;
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int iomap_size;
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