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88a404a2d1
Add a new microchipsw target aimed add supporting Microchip switch SoC-s. Start by supporting LAN969x SoC-s as the first subtarget. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
37 lines
1.7 KiB
Diff
37 lines
1.7 KiB
Diff
From 9f4b9996e892cd721bf1f6664c3ba95a7592924c Mon Sep 17 00:00:00 2001
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From: Daniel Machon <daniel.machon@microchip.com>
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Date: Fri, 4 Oct 2024 15:19:29 +0200
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Subject: [PATCH 31/82] net: sparx5: modify SPX5_PORTS_ALL macro
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In preparation for lan969x, we need to define the SPX5_PORTS_ALL macro
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as 70 (65 front ports + 5 internal ports). This is required as the
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SPX5_PORT_CPU will be redefined as an offset to the number of front
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ports, in a subsequent patch.
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Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
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Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
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Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
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Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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---
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drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h
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+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h
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@@ -52,13 +52,14 @@ enum sparx5_vlan_port_type {
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};
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#define SPX5_PORTS 65
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+#define SPX5_PORTS_ALL 70 /* Total number of ports */
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+
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#define SPX5_PORT_CPU (SPX5_PORTS) /* Next port is CPU port */
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#define SPX5_PORT_CPU_0 (SPX5_PORT_CPU + 0) /* CPU Port 65 */
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#define SPX5_PORT_CPU_1 (SPX5_PORT_CPU + 1) /* CPU Port 66 */
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#define SPX5_PORT_VD0 (SPX5_PORT_CPU + 2) /* VD0/Port 67 used for IPMC */
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#define SPX5_PORT_VD1 (SPX5_PORT_CPU + 3) /* VD1/Port 68 used for AFI/OAM */
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#define SPX5_PORT_VD2 (SPX5_PORT_CPU + 4) /* VD2/Port 69 used for IPinIP*/
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-#define SPX5_PORTS_ALL (SPX5_PORT_CPU + 5) /* Total number of ports */
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#define PGID_BASE SPX5_PORTS /* Starts after port PGIDs */
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#define PGID_UC_FLOOD (PGID_BASE + 0)
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