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88a404a2d1
Add a new microchipsw target aimed add supporting Microchip switch SoC-s. Start by supporting LAN969x SoC-s as the first subtarget. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
539 lines
14 KiB
Plaintext
539 lines
14 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
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/*
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* Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
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*/
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#include <dt-bindings/clock/microchip,lan969x.h>
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#include <dt-bindings/dma/at91.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mfd/at91-usart.h>
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#include <dt-bindings/mfd/atmel-flexcom.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "Microchip LAN969x";
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compatible = "microchip,lan969x";
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interrupt-parent = <&gic>;
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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clocks {
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fx100_clk: fx100-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <320000000>;
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};
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cpu_clk: cpu-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000000>;
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};
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ddr_clk: ddr-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <600000000>;
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};
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fabric_clk: fabric-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <250000000>;
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x0 0x0>;
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next-level-cache = <&l2_0>;
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};
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l2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Secure Phys IRQ */
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Non-secure Phys IRQ */
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virt IRQ */
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hyp IRQ */
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};
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axi: axi {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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usb: usb@300000 {
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compatible = "microchip,lan9691-dwc3", "snps,dwc3";
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reg = <0x300000 0x80000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks GCK_GATE_USB_DRD>,
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<&clks GCK_ID_USB_REFCLK>;
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clock-names = "bus_early", "ref";
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assigned-clocks = <&clks GCK_ID_USB_REFCLK>;
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assigned-clock-rates = <60000000>;
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maximum-speed = "high-speed";
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dr_mode = "host";
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status = "disabled";
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};
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otp: otp@e0021000 {
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compatible = "microchip,lan9691-otpc";
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reg = <0xe0021000 0x1000>;
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};
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flx0: flexcom@e0040000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe0040000 0x100>;
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clocks = <&clks GCK_ID_FLEXCOM0>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe0040000 0x800>;
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status = "disabled";
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usart0: serial@200 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0x200 0x200>;
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atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
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<&dma AT91_XDMAC_DT_PERID(2)>;
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dma-names = "tx", "rx";
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clocks = <&fabric_clk>;
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clock-names = "usart";
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atmel,fifo-size = <32>;
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status = "disabled";
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};
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spi0: spi@400 {
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compatible = "atmel,at91rm9200-spi";
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reg = <0x400 0x200>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
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<&dma AT91_XDMAC_DT_PERID(2)>;
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dma-names = "tx", "rx";
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clocks = <&fabric_clk>;
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clock-names = "spi_clk";
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atmel,fifo-size = <32>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c0: i2c@600 {
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compatible = "microchip,sam9x60-i2c";
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reg = <0x600 0x200>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
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<&dma AT91_XDMAC_DT_PERID(2)>;
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dma-names = "tx", "rx";
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clocks = <&fabric_clk>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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flx1: flexcom@e0044000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe0044000 0x100>;
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clocks = <&clks GCK_ID_FLEXCOM1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe0044000 0x800>;
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status = "disabled";
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usart1: serial@200 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0x200 0x200>;
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atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
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<&dma AT91_XDMAC_DT_PERID(2)>;
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dma-names = "tx", "rx";
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clocks = <&fabric_clk>;
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clock-names = "usart";
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atmel,fifo-size = <32>;
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status = "disabled";
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};
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spi1: spi@400 {
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compatible = "atmel,at91rm9200-spi";
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reg = <0x400 0x200>;
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
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<&dma AT91_XDMAC_DT_PERID(2)>;
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dma-names = "tx", "rx";
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clocks = <&fabric_clk>;
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clock-names = "spi_clk";
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atmel,fifo-size = <32>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@600 {
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compatible = "microchip,sam9x60-i2c";
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reg = <0x600 0x200>;
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
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<&dma AT91_XDMAC_DT_PERID(2)>;
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dma-names = "tx", "rx";
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clocks = <&fabric_clk>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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trng: rng@e0048000 {
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compatible = "atmel,at91sam9g45-trng";
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reg = <0xe0048000 0x100>;
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clocks = <&fabric_clk>;
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status = "disabled";
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};
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aes: crypto@e004c000 {
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compatible = "atmel,at91sam9g46-aes";
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reg = <0xe004c000 0x100>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma AT91_XDMAC_DT_PERID(12)>,
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<&dma AT91_XDMAC_DT_PERID(13)>;
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dma-names = "tx", "rx";
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clocks = <&fabric_clk>;
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clock-names = "aes_clk";
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status = "disabled";
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};
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flx2: flexcom@e0060000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe0060000 0x100>;
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clocks = <&clks GCK_ID_FLEXCOM2>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe0060000 0x800>;
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status = "disabled";
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usart2: serial@200 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0x200 0x200>;
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atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma AT91_XDMAC_DT_PERID(7)>,
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<&dma AT91_XDMAC_DT_PERID(6)>;
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dma-names = "tx", "rx";
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clocks = <&fabric_clk>;
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clock-names = "usart";
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atmel,fifo-size = <32>;
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status = "disabled";
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};
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spi2: spi@400 {
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compatible = "atmel,at91rm9200-spi";
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reg = <0x400 0x200>;
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma AT91_XDMAC_DT_PERID(7)>,
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<&dma AT91_XDMAC_DT_PERID(6)>;
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dma-names = "tx", "rx";
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clocks = <&fabric_clk>;
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clock-names = "spi_clk";
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atmel,fifo-size = <32>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@600 {
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compatible = "microchip,sam9x60-i2c";
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reg = <0x600 0x200>;
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&fabric_clk>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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flx3: flexcom@e0064000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe0064000 0x100>;
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clocks = <&clks GCK_ID_FLEXCOM3>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe0064000 0x800>;
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status = "disabled";
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usart3: serial@200 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0x200 0x200>;
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atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma AT91_XDMAC_DT_PERID(9)>,
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<&dma AT91_XDMAC_DT_PERID(8)>;
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dma-names = "tx", "rx";
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clocks = <&fabric_clk>;
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clock-names = "usart";
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atmel,fifo-size = <32>;
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status = "disabled";
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};
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spi3: spi@400 {
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compatible = "atmel,at91rm9200-spi";
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reg = <0x400 0x200>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma AT91_XDMAC_DT_PERID(9)>,
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<&dma AT91_XDMAC_DT_PERID(8)>;
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dma-names = "tx", "rx";
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clocks = <&fabric_clk>;
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clock-names = "spi_clk";
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atmel,fifo-size = <32>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c3: i2c@600 {
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compatible = "microchip,sam9x60-i2c";
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reg = <0x600 0x200>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma AT91_XDMAC_DT_PERID(9)>,
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<&dma AT91_XDMAC_DT_PERID(8)>;
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dma-names = "tx", "rx";
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clocks = <&fabric_clk>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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dma: dma-controller@e0068000 {
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compatible = "microchip,sama7g5-dma";
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reg = <0xe0068000 0x1000>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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dma-channels = <16>;
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#dma-cells = <1>;
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clocks = <&fabric_clk>;
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clock-names = "dma_clk";
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};
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sha: crypto@e006c000 {
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compatible = "atmel,at91sam9g46-sha";
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reg = <0xe006c000 0xec>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma AT91_XDMAC_DT_PERID(14)>;
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dma-names = "tx";
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clocks = <&fabric_clk>;
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clock-names = "sha_clk";
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status = "disabled";
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};
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timer: timer@e008c000 {
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compatible = "snps,dw-apb-timer";
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reg = <0xe008c000 0x400>;
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clocks = <&fabric_clk>;
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clock-names = "timer";
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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watchdog: watchdog@e0090000 {
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compatible = "snps,dw-wdt";
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reg = <0xe0090000 0x1000>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&fabric_clk>;
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};
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cpu_ctrl: syscon@e00c0000 {
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compatible = "microchip,lan966x-cpu-syscon", "syscon";
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reg = <0xe00c0000 0x350>;
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};
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switch: switch@e00c0000 {
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compatible = "microchip,lan9691-switch";
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reg = <0xe00c0000 0x0010000>,
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<0xe2010000 0x1410000>;
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reg-names = "cpu", "devices";
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interrupt-names = "xtr", "fdma", "ptp";
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&reset 0>;
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reset-names = "switch";
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status = "disabled";
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};
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clks: clock-controller@e00c00b4 {
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compatible = "microchip,lan9691-gck";
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#clock-cells = <1>;
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clocks = <&cpu_clk>, <&ddr_clk>, <&fx100_clk>;
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clock-names = "cpu", "ddr", "sys";
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reg = <0xe00c00b4 0x30>, <0xe00c0308 0x4>;
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};
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qspi0: spi@e0804000 {
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compatible = "microchip,lan9691-qspi";
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reg = <0xe0804000 0x00000100>,
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<0x20000000 0x08000000>;
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reg-names = "qspi_base", "qspi_mmap";
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&fabric_clk>, <&clks GCK_ID_QSPI0>;
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clock-names = "pclk", "gclk";
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assigned-clocks = <&clks GCK_ID_QSPI0>;
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assigned-clock-rates = <100000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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sdmmc0: mmc@e0830000 {
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compatible = "microchip,lan9691-sdhci";
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reg = <0xe0830000 0x00000300>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks GCK_ID_SDMMC0>, <&clks GCK_ID_SDMMC0>;
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clock-names = "hclock", "multclk";
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assigned-clocks = <&clks GCK_ID_SDMMC0>;
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assigned-clock-rates = <100000000>;
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status = "disabled";
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};
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sdmmc1: mmc@e0838000 {
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compatible = "microchip,lan9691-sdhci";
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reg = <0xe0838000 0x00000300>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks GCK_ID_SDMMC1>, <&clks GCK_ID_SDMMC1>;
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clock-names = "hclock", "multclk";
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assigned-clocks = <&clks GCK_ID_SDMMC1>;
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assigned-clock-rates = <45000000>;
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status = "disabled";
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};
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qspi2: spi@e0834000 {
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compatible = "microchip,lan9691-qspi";
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reg = <0xe0834000 0x00000100>,
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<0x30000000 0x04000000>;
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reg-names = "qspi_base", "qspi_mmap";
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&fabric_clk>, <&clks GCK_ID_QSPI2>;
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clock-names = "pclk", "gclk";
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assigned-clocks = <&clks GCK_ID_QSPI2>;
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assigned-clock-rates = <100000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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reset: reset-controller@e201000c {
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compatible = "microchip,lan9691-switch-reset", "microchip,lan966x-switch-reset";
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reg = <0xe201000c 0x4>;
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reg-names = "gcb";
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#reset-cells = <1>;
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cpu-syscon = <&cpu_ctrl>;
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};
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gpio: pinctrl@e20100d4 {
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compatible = "microchip,lan9691-pinctrl";
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reg = <0xe20100d4 0xd4>,
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<0xe2010370 0xa8>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&gpio 0 0 66>;
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interrupt-controller;
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|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
mdio0: mdio@e20101a8 {
|
|
compatible = "mscc,ocelot-miim";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xe20101a8 0x24>;
|
|
clocks = <&fx100_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mdio1: mdio@e20101cc {
|
|
compatible = "mscc,ocelot-miim";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xe20101cc 0x24>;
|
|
clocks = <&fx100_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sgpio: gpio@e2010230 {
|
|
compatible = "microchip,sparx5-sgpio";
|
|
reg = <0xe2010230 0x118>;
|
|
clocks = <&fx100_clk>;
|
|
resets = <&reset 0>;
|
|
reset-names = "switch";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
sgpio_in: gpio@0 {
|
|
compatible = "microchip,sparx5-sgpio-bank";
|
|
reg = <0>;
|
|
gpio-controller;
|
|
#gpio-cells = <3>;
|
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
};
|
|
|
|
sgpio_out: gpio@1 {
|
|
compatible = "microchip,sparx5-sgpio-bank";
|
|
reg = <1>;
|
|
gpio-controller;
|
|
#gpio-cells = <3>;
|
|
};
|
|
};
|
|
|
|
tmon: hwmon@e2020100 {
|
|
compatible = "microchip,sparx5-temp";
|
|
reg = <0xe2020100 0xc>;
|
|
clocks = <&fx100_clk>;
|
|
#thermal-sensor-cells = <0>;
|
|
};
|
|
|
|
serdes: serdes@e3410000 {
|
|
compatible = "microchip,lan9691-serdes";
|
|
#phy-cells = <1>;
|
|
clocks = <&fabric_clk>;
|
|
reg = <0xe3410000 0x150000>;
|
|
};
|
|
|
|
gic: interrupt-controller@e8c11000 {
|
|
compatible = "arm,gic-400";
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
reg = <0xe8c11000 0x1000>, /* Distributor GICD_ */
|
|
<0xe8c12000 0x2000>, /* CPU interface GICC_ */
|
|
<0xe8c14000 0x2000>, /* Virt interface control */
|
|
<0xe8c16000 0x2000>; /* Virt CPU interface */
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
};
|