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61 lines
1.5 KiB
ArmAsm
61 lines
1.5 KiB
ArmAsm
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#define IFX_CACHE_EXTRA_INVALID_TAG \
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mtc0 zero, CP0_TAGLO, 1; \
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mtc0 zero, CP0_TAGLO, 2; \
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mtc0 zero, CP0_TAGLO, 3; \
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mtc0 zero, CP0_TAGLO, 4;
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#define IFX_CACHE_EXTRA_OPERATION \
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/* set WST bit */ \
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mfc0 a0, CP0_ECC; \
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li a1, ECCF_WST; \
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or a0, a1; \
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mtc0 a0, CP0_ECC; \
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\
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li a0, K0BASE; \
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move a2, t2; /* icacheSize */ \
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move a3, t4; /* icacheLineSize */ \
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move a1, a2; \
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icacheop(a0,a1,a2,a3,(Index_Store_Tag_I)); \
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\
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/* clear WST bit */ \
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mfc0 a0, CP0_ECC; \
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li a1, ~ECCF_WST; \
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and a0, a1; \
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mtc0 a0, CP0_ECC; \
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\
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/* 1: initialise dcache tags. */ \
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\
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/* cache line size */ \
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li a2, CFG_CACHELINE_SIZE; \
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/* kseg0 mem address */ \
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li a1, 0; \
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li a3, CFG_CACHE_SETS * CFG_CACHE_WAYS; \
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1: \
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/* store tag (invalid, not locked) */ \
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cache 0x8, 0(a1); \
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cache 0x9, 0(a1); \
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\
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add a3, -1; \
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bne a3, zero, 1b; \
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add a1, a2; \
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\
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/* set WST bit */ \
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mfc0 a0, CP0_ECC; \
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li a1, ECCF_WST; \
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or a0, a1; \
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mtc0 a0, CP0_ECC; \
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\
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li a0, K0BASE; \
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move a2, t3; /* dcacheSize */ \
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move a3, t5; /* dcacheLineSize */ \
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move a1, a2; \
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icacheop(a0,a1,a2,a3,(Index_Store_Tag_D)); \
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\
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/* clear WST bit */ \
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mfc0 a0, CP0_ECC; \
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li a1, ~ECCF_WST; \
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and a0, a1; \
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mtc0 a0, CP0_ECC;
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