Robert Marko 845caa8d46 qualcommax: 301w: correct AQR reset GPIO-s ... It seems that the reset GPIO-s defined for the two AQR PHY-s are actually reversed. Manually testing confirmed that GPIO44 is actually reset GPIO of AQR at 0, while GPIO59 is reset of AQR at 8: root@OpenWrt:~# mdio 9* DEV PHY-ID LINK 0x00 0x00000000 down 0x08 0x00000000 down 0x10 0x004dd0b1 down 0x11 0x004dd0b1 down 0x12 0x004dd0b1 down 0x13 0x004dd0b1 up 0x14 0x004dd0b1 down 0x15 0x04820a05 down root@OpenWrt:~# gpioset gpiochip0 44=0 root@OpenWrt:~# mdio 9* DEV PHY-ID LINK 0x08 0x00000000 down 0x10 0x004dd0b1 down 0x11 0x004dd0b1 down 0x12 0x004dd0b1 down 0x13 0x004dd0b1 up 0x14 0x004dd0b1 down 0x15 0x04820a05 down root@OpenWrt:~# gpioset gpiochip0 44=1 root@OpenWrt:~# mdio 9* DEV PHY-ID LINK 0x00 0x00000000 down 0x08 0x00000000 down 0x10 0x004dd0b1 down 0x11 0x004dd0b1 down 0x12 0x004dd0b1 down 0x13 0x004dd0b1 up 0x14 0x004dd0b1 down 0x15 0x04820a05 down root@OpenWrt:~# gpioset gpiochip0 59=0 root@OpenWrt:~# mdio 9* DEV PHY-ID LINK 0x00 0x00000000 down 0x10 0x004dd0b1 down 0x11 0x004dd0b1 down 0x12 0x004dd0b1 down 0x13 0x004dd0b1 up 0x14 0x004dd0b1 down 0x15 0x04820a05 down root@OpenWrt:~# gpioset gpiochip0 59=1 root@OpenWrt:~# mdio 9* DEV PHY-ID LINK 0x00 0x00000000 down 0x08 0x00000000 down 0x10 0x004dd0b1 down 0x11 0x004dd0b1 down 0x12 0x004dd0b1 down 0x13 0x004dd0b1 up 0x14 0x004dd0b1 down 0x15 0x04820a05 down Signed-off-by: Robert Marko <robimarko@gmail.com>		2024-01-26 15:30:02 +01:00
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files	qualcommax: 301w: correct AQR reset GPIO-s	2024-01-26 15:30:02 +01:00
image	ipq807x: prpl-haze: enable LED driver on device tree	2024-01-15 16:59:57 +01:00
ipq807x	qualcommax: add SMP affinity script	2024-01-22 15:37:11 +01:00
patches-6.1	qualcommax: refresh 6.1 patches	2024-01-26 10:19:40 +01:00
config-6.1	qualcommax: ipq807x: move subtarget specific kernel options	2023-11-02 20:25:33 +01:00
Makefile