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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
29 lines
873 B
Diff
29 lines
873 B
Diff
From f7ab709727e845ffdfc428ec2f236d0c1997b153 Mon Sep 17 00:00:00 2001
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From: Emil Renner Berthing <kernel@esmil.dk>
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Date: Sat, 20 Nov 2021 21:33:08 +0100
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Subject: [PATCH 1023/1024] RISC-V: Add StarFive JH7100 audio reset node
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Add device tree node for the audio resets on the StarFive JH7100 RISC-V
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SoC.
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Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
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---
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arch/riscv/boot/dts/starfive/jh7100.dtsi | 6 ++++++
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1 file changed, 6 insertions(+)
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--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
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+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
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@@ -144,6 +144,12 @@
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#clock-cells = <1>;
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};
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+ audrst: reset-controller@10490000 {
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+ compatible = "starfive,jh7100-audrst";
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+ reg = <0x0 0x10490000 0x0 0x10000>;
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+ #reset-cells = <1>;
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+ };
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+
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clkgen: clock-controller@11800000 {
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compatible = "starfive,jh7100-clkgen";
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reg = <0x0 0x11800000 0x0 0x10000>;
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