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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
31 lines
1.1 KiB
Diff
31 lines
1.1 KiB
Diff
From 3b83b32e16fa431c76a5da1ac59c268ca2fecbb5 Mon Sep 17 00:00:00 2001
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From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Date: Sat, 11 Feb 2023 05:18:11 +0200
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Subject: [PATCH 1017/1024] dt-bindings: riscv: sifive-ccache: Add
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'uncached-offset' property
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Add the 'uncached-offset' property to be used for specifying the
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uncached memory offset required for handling non-coherent DMA
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transactions.
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Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Link: https://lore.kernel.org/r/20230211031821.976408-3-cristian.ciocaltea@collabora.com
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---
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Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml | 5 +++++
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1 file changed, 5 insertions(+)
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--- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
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+++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
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@@ -70,6 +70,11 @@ properties:
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next-level-cache: true
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+ uncached-offset:
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+ $ref: /schemas/types.yaml#/definitions/uint64
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+ description: |
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+ Uncached memory offset for handling non-coherent DMA transactions.
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+
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memory-region:
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maxItems: 1
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description: |
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