mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2025-11-03 22:44:27 -05:00
4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
41 lines
1.5 KiB
Diff
41 lines
1.5 KiB
Diff
From 790e1157753b4dcc9bad4521987fe09aa6657876 Mon Sep 17 00:00:00 2001
|
|
From: Geert Uytterhoeven <geert@linux-m68k.org>
|
|
Date: Thu, 25 Nov 2021 14:21:18 +0100
|
|
Subject: [PATCH 1003/1024] riscv: dts: starfive: Group tuples in interrupt
|
|
properties
|
|
|
|
To improve human readability and enable automatic validation, the tuples
|
|
in the various properties containing interrupt specifiers should be
|
|
grouped.
|
|
|
|
Fix this by grouping the tuples of "interrupts-extended" properties
|
|
using angle brackets.
|
|
|
|
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
|
|
---
|
|
arch/riscv/boot/dts/starfive/jh7100.dtsi | 8 ++++----
|
|
1 file changed, 4 insertions(+), 4 deletions(-)
|
|
|
|
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
|
|
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
|
|
@@ -118,15 +118,15 @@
|
|
clint: clint@2000000 {
|
|
compatible = "starfive,jh7100-clint", "sifive,clint0";
|
|
reg = <0x0 0x2000000 0x0 0x10000>;
|
|
- interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
|
|
- &cpu1_intc 3 &cpu1_intc 7>;
|
|
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
|
|
+ <&cpu1_intc 3>, <&cpu1_intc 7>;
|
|
};
|
|
|
|
plic: interrupt-controller@c000000 {
|
|
compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
|
|
reg = <0x0 0xc000000 0x0 0x4000000>;
|
|
- interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9
|
|
- &cpu1_intc 11 &cpu1_intc 9>;
|
|
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
|
|
+ <&cpu1_intc 11>, <&cpu1_intc 9>;
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|