mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2025-10-31 14:04:26 -04:00
c62d86ecb8
This watchdog driver should work with SoC having a PMU. This fixes #11720. SVN-Revision: 34323
132 lines
3.7 KiB
Diff
132 lines
3.7 KiB
Diff
--- a/drivers/ssb/driver_chipcommon.c
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+++ b/drivers/ssb/driver_chipcommon.c
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@@ -4,6 +4,7 @@
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*
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* Copyright 2005, Broadcom Corporation
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* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
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+ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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@@ -12,6 +13,7 @@
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#include <linux/ssb/ssb_regs.h>
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#include <linux/export.h>
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#include <linux/pci.h>
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+#include <linux/bcm47xx_wdt.h>
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#include "ssb_private.h"
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@@ -306,6 +308,43 @@ static u32 ssb_chipco_watchdog_get_max_t
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return (1 << nb) - 1;
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}
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+u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
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+{
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+ struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
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+
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+ if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
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+ return 0;
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+
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+ return ssb_chipco_watchdog_timer_set(cc, ticks);
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+}
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+
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+u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
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+{
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+ struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
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+ u32 ticks;
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+
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+ if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
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+ return 0;
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+
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+ ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
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+ return ticks / cc->ticks_per_ms;
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+}
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+
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+static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
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+{
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+ struct ssb_bus *bus = cc->dev->bus;
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+
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+ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
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+ /* based on 32KHz ILP clock */
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+ return 32;
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+ } else {
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+ if (cc->dev->id.revision < 18)
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+ return ssb_clockspeed(bus) / 1000;
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+ else
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+ return ssb_chipco_alp_clock(cc) / 1000;
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+ }
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+}
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+
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void ssb_chipcommon_init(struct ssb_chipcommon *cc)
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{
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if (!cc->dev)
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@@ -323,6 +362,11 @@ void ssb_chipcommon_init(struct ssb_chip
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chipco_powercontrol_init(cc);
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ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
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calc_fast_powerup_delay(cc);
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+
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+ if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
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+ cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
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+ cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
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+ }
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}
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void ssb_chipco_suspend(struct ssb_chipcommon *cc)
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@@ -421,7 +465,7 @@ void ssb_chipco_timing_init(struct ssb_c
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}
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/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
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-void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
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+u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
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{
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u32 maxt;
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enum ssb_clkmode clkmode;
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@@ -441,6 +485,7 @@ void ssb_chipco_watchdog_timer_set(struc
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/* instant NMI */
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chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
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}
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+ return ticks;
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}
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void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
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--- a/drivers/ssb/ssb_private.h
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+++ b/drivers/ssb/ssb_private.h
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@@ -3,6 +3,7 @@
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#include <linux/ssb/ssb.h>
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#include <linux/types.h>
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+#include <linux/bcm47xx_wdt.h>
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#define PFX "ssb: "
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@@ -226,4 +227,8 @@ static inline int ssb_sflash_init(struct
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extern struct platform_device ssb_pflash_dev;
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+extern u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
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+ u32 ticks);
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+extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
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+
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#endif /* LINUX_SSB_PRIVATE_H_ */
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--- a/include/linux/ssb/ssb_driver_chipcommon.h
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+++ b/include/linux/ssb/ssb_driver_chipcommon.h
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@@ -607,6 +607,8 @@ struct ssb_chipcommon {
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#ifdef CONFIG_SSB_SFLASH
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struct bcm47xx_sflash sflash;
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#endif
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+ u32 ticks_per_ms;
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+ u32 max_timer_ms;
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};
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static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
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@@ -646,8 +648,7 @@ enum ssb_clkmode {
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extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
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enum ssb_clkmode mode);
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-extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
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- u32 ticks);
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+extern u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks);
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void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
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