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The GW16083 Ethernet Expansion Mezzanine adds the following to supported Gateworks baseboards: * 7-port Ethernet Switch * 4x RJ45 ports (ENET1-4) supporing 802.11af/at PoE (with optional PoE module) * 2x RJ45 ports or SFP module (ENET5-6) (auto-selected) This series adds support for a phy driver that adds support for ENET5/ENET6 PHY adding initialization for those PHY's and a polling mechanism that detects SFP insertion and configuration. Signed-off-by: Tim Harvey <tharvey@gateworks.com> SVN-Revision: 42147
130 lines
3.5 KiB
Diff
130 lines
3.5 KiB
Diff
Author: Tim Harvey <tharvey@gateworks.com>
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Date: Thu May 15 00:12:26 2014 -0700
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net: igb: add i210/i211 support for phy read/write
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The i210/i211 uses the MDICNFG register for the phy address instead of the
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MDIC register.
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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--- a/drivers/net/ethernet/intel/igb/e1000_phy.c
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+++ b/drivers/net/ethernet/intel/igb/e1000_phy.c
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@@ -139,7 +139,7 @@ out:
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s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
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{
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struct e1000_phy_info *phy = &hw->phy;
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- u32 i, mdic = 0;
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+ u32 i, mdicnfg, mdic = 0;
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s32 ret_val = 0;
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if (offset > MAX_PHY_REG_ADDRESS) {
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@@ -152,11 +152,25 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
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* Control register. The MAC will take care of interfacing with the
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* PHY to retrieve the desired data.
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*/
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- mdic = ((offset << E1000_MDIC_REG_SHIFT) |
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- (phy->addr << E1000_MDIC_PHY_SHIFT) |
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- (E1000_MDIC_OP_READ));
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+ switch (hw->mac.type) {
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+ case e1000_i210:
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+ case e1000_i211:
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+ mdicnfg = rd32(E1000_MDICNFG);
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+ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
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+ mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
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+ wr32(E1000_MDICNFG, mdicnfg);
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+ mdic = ((offset << E1000_MDIC_REG_SHIFT) |
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+ (E1000_MDIC_OP_READ));
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+ break;
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+ default:
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+ mdic = ((offset << E1000_MDIC_REG_SHIFT) |
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+ (phy->addr << E1000_MDIC_PHY_SHIFT) |
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+ (E1000_MDIC_OP_READ));
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+ break;
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+ }
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wr32(E1000_MDIC, mdic);
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+ wrfl();
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/* Poll the ready bit to see if the MDI read completed
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* Increasing the time out as testing showed failures with
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@@ -181,6 +195,18 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
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*data = (u16) mdic;
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out:
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+ switch (hw->mac.type) {
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+ /* restore MDICNFG to have phy's addr */
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+ case e1000_i210:
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+ case e1000_i211:
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+ mdicnfg = rd32(E1000_MDICNFG);
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+ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
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+ mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT);
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+ wr32(E1000_MDICNFG, mdicnfg);
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+ break;
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+ default:
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+ break;
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+ }
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return ret_val;
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}
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@@ -195,7 +221,7 @@ out:
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s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
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{
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struct e1000_phy_info *phy = &hw->phy;
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- u32 i, mdic = 0;
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+ u32 i, mdicnfg, mdic = 0;
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s32 ret_val = 0;
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if (offset > MAX_PHY_REG_ADDRESS) {
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@@ -208,12 +234,27 @@ s32 igb_write_phy_reg_mdic(struct e1000_
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* Control register. The MAC will take care of interfacing with the
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* PHY to retrieve the desired data.
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*/
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- mdic = (((u32)data) |
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- (offset << E1000_MDIC_REG_SHIFT) |
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- (phy->addr << E1000_MDIC_PHY_SHIFT) |
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- (E1000_MDIC_OP_WRITE));
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+ switch (hw->mac.type) {
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+ case e1000_i210:
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+ case e1000_i211:
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+ mdicnfg = rd32(E1000_MDICNFG);
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+ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
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+ mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
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+ wr32(E1000_MDICNFG, mdicnfg);
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+ mdic = (((u32)data) |
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+ (offset << E1000_MDIC_REG_SHIFT) |
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+ (E1000_MDIC_OP_WRITE));
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+ break;
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+ default:
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+ mdic = (((u32)data) |
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+ (offset << E1000_MDIC_REG_SHIFT) |
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+ (phy->addr << E1000_MDIC_PHY_SHIFT) |
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+ (E1000_MDIC_OP_WRITE));
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+ break;
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+ }
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wr32(E1000_MDIC, mdic);
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+ wrfl();
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/* Poll the ready bit to see if the MDI read completed
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* Increasing the time out as testing showed failures with
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@@ -237,6 +278,18 @@ s32 igb_write_phy_reg_mdic(struct e1000_
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}
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out:
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+ switch (hw->mac.type) {
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+ /* restore MDICNFG to have phy's addr */
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+ case e1000_i210:
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+ case e1000_i211:
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+ mdicnfg = rd32(E1000_MDICNFG);
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+ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
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+ mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT);
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+ wr32(E1000_MDICNFG, mdicnfg);
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+ break;
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+ default:
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+ break;
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+ }
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return ret_val;
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}
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