mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2025-10-31 05:54:26 -04:00
9300eda00f
replace our downstream version of the patches with the ones that were sent upstream. Signed-off-by: John Crispin <john@phrozen.org>
61 lines
1.6 KiB
Diff
61 lines
1.6 KiB
Diff
--- a/drivers/spi/spi-ath79.c
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+++ b/drivers/spi/spi-ath79.c
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@@ -101,9 +101,6 @@ static void ath79_spi_enable(struct ath7
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/* save CTRL register */
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sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
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sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
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-
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- /* TODO: setup speed? */
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- ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
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}
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static void ath79_spi_disable(struct ath79_spi *sp)
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@@ -203,6 +200,38 @@ static u32 ath79_spi_txrx_mode0(struct s
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return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
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}
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+static bool ath79_spi_flash_read_supported(struct spi_device *spi)
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+{
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+ if (spi->chip_select || gpio_is_valid(spi->cs_gpio))
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+ return false;
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+
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+ return true;
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+}
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+
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+static int ath79_spi_read_flash_data(struct spi_device *spi,
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+ struct spi_flash_read_message *msg)
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+{
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+ struct ath79_spi *sp = ath79_spidev_to_sp(spi);
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+
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+ if (msg->addr_width > 3)
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+ return -EOPNOTSUPP;
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+
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+ /* disable GPIO mode */
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+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
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+
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+ memcpy_fromio(msg->buf, sp->base + msg->from, msg->len);
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+
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+ /* enable GPIO mode */
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+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
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+
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+ /* restore IOC register */
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+ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
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+
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+ msg->retlen = msg->len;
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+
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+ return 0;
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+}
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+
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static int ath79_spi_probe(struct platform_device *pdev)
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{
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struct spi_master *master;
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@@ -237,6 +266,8 @@ static int ath79_spi_probe(struct platfo
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ret = PTR_ERR(sp->base);
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goto err_put_master;
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}
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+ master->spi_flash_read = ath79_spi_read_flash_data;
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+ master->flash_read_supported = ath79_spi_flash_read_supported;
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sp->clk = devm_clk_get(&pdev->dev, "ahb");
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if (IS_ERR(sp->clk)) {
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