mirror of
git://git.openwrt.org/openwrt/openwrt.git
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9300eda00f
replace our downstream version of the patches with the ones that were sent upstream. Signed-off-by: John Crispin <john@phrozen.org>
244 lines
8.2 KiB
Diff
244 lines
8.2 KiB
Diff
From 288a8eb0d41f09fda242e05f8a7bd1f5b3489477 Mon Sep 17 00:00:00 2001
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From: Felix Fietkau <nbd@nbd.name>
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Date: Tue, 6 Mar 2018 13:19:26 +0100
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Subject: [PATCH 21/33] MIPS: ath79: add helpers for setting clocks and expose
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the ref clock
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Preparation for transitioning the legacy clock setup code over
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to OF.
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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arch/mips/ath79/clock.c | 128 ++++++++++++++++++----------------
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include/dt-bindings/clock/ath79-clk.h | 3 +-
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2 files changed, 68 insertions(+), 63 deletions(-)
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--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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@@ -37,20 +37,46 @@ static struct clk_onecell_data clk_data
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.clk_num = ARRAY_SIZE(clks),
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};
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-static struct clk *__init ath79_add_sys_clkdev(
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- const char *id, unsigned long rate)
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+static const char * const clk_names[ATH79_CLK_END] = {
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+ [ATH79_CLK_CPU] = "cpu",
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+ [ATH79_CLK_DDR] = "ddr",
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+ [ATH79_CLK_AHB] = "ahb",
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+ [ATH79_CLK_REF] = "ref",
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+};
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+
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+static const char * __init ath79_clk_name(int type)
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{
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- struct clk *clk;
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- int err;
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+ BUG_ON(type >= ARRAY_SIZE(clk_names) || !clk_names[type]);
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+ return clk_names[type];
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+}
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- clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
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+static void __init __ath79_set_clk(int type, const char *name, struct clk *clk)
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+{
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if (IS_ERR(clk))
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- panic("failed to allocate %s clock structure", id);
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+ panic("failed to allocate %s clock structure", clk_names[type]);
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- err = clk_register_clkdev(clk, id, NULL);
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- if (err)
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- panic("unable to register %s clock device", id);
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+ clks[type] = clk;
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+ clk_register_clkdev(clk, name, NULL);
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+}
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+static struct clk * __init ath79_set_clk(int type, unsigned long rate)
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+{
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+ const char *name = ath79_clk_name(type);
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+ struct clk *clk;
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+
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+ clk = clk_register_fixed_rate(NULL, name, NULL, 0, rate);
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+ __ath79_set_clk(type, name, clk);
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+ return clk;
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+}
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+
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+static struct clk * __init ath79_set_ff_clk(int type, const char *parent,
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+ unsigned int mult, unsigned int div)
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+{
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+ const char *name = ath79_clk_name(type);
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+ struct clk *clk;
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+
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+ clk = clk_register_fixed_factor(NULL, name, parent, 0, mult, div);
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+ __ath79_set_clk(type, name, clk);
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return clk;
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}
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@@ -80,27 +106,15 @@ static void __init ar71xx_clocks_init(vo
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div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
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ahb_rate = cpu_rate / div;
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- ath79_add_sys_clkdev("ref", ref_rate);
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- clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
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- clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
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- clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
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+ ath79_set_clk(ATH79_CLK_REF, ref_rate);
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+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
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+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
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+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
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clk_add_alias("wdt", NULL, "ahb", NULL);
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clk_add_alias("uart", NULL, "ahb", NULL);
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}
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-static struct clk * __init ath79_reg_ffclk(const char *name,
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- const char *parent_name, unsigned int mult, unsigned int div)
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-{
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- struct clk *clk;
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-
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- clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
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- if (IS_ERR(clk))
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- panic("failed to allocate %s clock structure", name);
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-
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- return clk;
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-}
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-
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static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
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{
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u32 pll;
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@@ -114,24 +128,19 @@ static void __init ar724x_clk_init(struc
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ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
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ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
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- clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", mult, div);
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- clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", mult, div * ddr_div);
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- clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", mult, div * ahb_div);
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+ ath79_set_ff_clk(ATH79_CLK_CPU, "ref", mult, div);
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+ ath79_set_ff_clk(ATH79_CLK_DDR, "ref", mult, div * ddr_div);
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+ ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
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}
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static void __init ar724x_clocks_init(void)
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{
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struct clk *ref_clk;
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- ref_clk = ath79_add_sys_clkdev("ref", AR724X_BASE_FREQ);
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+ ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
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ar724x_clk_init(ref_clk, ath79_pll_base);
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- /* just make happy plat_time_init() from arch/mips/ath79/setup.c */
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- clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
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- clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
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- clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
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-
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clk_add_alias("wdt", NULL, "ahb", NULL);
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clk_add_alias("uart", NULL, "ahb", NULL);
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}
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@@ -186,12 +195,12 @@ static void __init ar9330_clk_init(struc
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AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
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}
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- clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref",
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- ninit_mul, ref_div * out_div * cpu_div);
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- clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref",
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- ninit_mul, ref_div * out_div * ddr_div);
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- clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref",
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- ninit_mul, ref_div * out_div * ahb_div);
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+ ath79_set_ff_clk(ATH79_CLK_CPU, "ref", ninit_mul,
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+ ref_div * out_div * cpu_div);
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+ ath79_set_ff_clk(ATH79_CLK_DDR, "ref", ninit_mul,
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+ ref_div * out_div * ddr_div);
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+ ath79_set_ff_clk(ATH79_CLK_AHB, "ref", ninit_mul,
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+ ref_div * out_div * ahb_div);
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}
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static void __init ar933x_clocks_init(void)
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@@ -206,15 +215,10 @@ static void __init ar933x_clocks_init(vo
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else
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ref_rate = (25 * 1000 * 1000);
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- ref_clk = ath79_add_sys_clkdev("ref", ref_rate);
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+ ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
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ar9330_clk_init(ref_clk, ath79_pll_base);
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- /* just make happy plat_time_init() from arch/mips/ath79/setup.c */
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- clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
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- clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
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- clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
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-
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clk_add_alias("wdt", NULL, "ahb", NULL);
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clk_add_alias("uart", NULL, "ref", NULL);
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}
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@@ -344,10 +348,10 @@ static void __init ar934x_clocks_init(vo
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else
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ahb_rate = cpu_pll / (postdiv + 1);
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- ath79_add_sys_clkdev("ref", ref_rate);
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- clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
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- clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
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- clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
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+ ath79_set_clk(ATH79_CLK_REF, ref_rate);
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+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
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+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
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+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
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clk_add_alias("wdt", NULL, "ref", NULL);
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clk_add_alias("uart", NULL, "ref", NULL);
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@@ -431,10 +435,10 @@ static void __init qca953x_clocks_init(v
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else
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ahb_rate = cpu_pll / (postdiv + 1);
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- ath79_add_sys_clkdev("ref", ref_rate);
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- ath79_add_sys_clkdev("cpu", cpu_rate);
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- ath79_add_sys_clkdev("ddr", ddr_rate);
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- ath79_add_sys_clkdev("ahb", ahb_rate);
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+ ath79_set_clk(ATH79_CLK_REF, ref_rate);
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+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
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+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
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+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
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clk_add_alias("wdt", NULL, "ref", NULL);
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clk_add_alias("uart", NULL, "ref", NULL);
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@@ -516,10 +520,10 @@ static void __init qca955x_clocks_init(v
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else
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ahb_rate = cpu_pll / (postdiv + 1);
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- ath79_add_sys_clkdev("ref", ref_rate);
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- clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
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- clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
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- clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
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+ ath79_set_clk(ATH79_CLK_REF, ref_rate);
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+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
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+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
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+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
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clk_add_alias("wdt", NULL, "ref", NULL);
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clk_add_alias("uart", NULL, "ref", NULL);
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@@ -620,10 +624,10 @@ static void __init qca956x_clocks_init(v
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else
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ahb_rate = cpu_pll / (postdiv + 1);
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- ath79_add_sys_clkdev("ref", ref_rate);
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- ath79_add_sys_clkdev("cpu", cpu_rate);
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- ath79_add_sys_clkdev("ddr", ddr_rate);
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- ath79_add_sys_clkdev("ahb", ahb_rate);
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+ ath79_set_clk(ATH79_CLK_REF, ref_rate);
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+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
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+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
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+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
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clk_add_alias("wdt", NULL, "ref", NULL);
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clk_add_alias("uart", NULL, "ref", NULL);
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--- a/include/dt-bindings/clock/ath79-clk.h
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+++ b/include/dt-bindings/clock/ath79-clk.h
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@@ -13,7 +13,8 @@
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#define ATH79_CLK_CPU 0
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#define ATH79_CLK_DDR 1
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#define ATH79_CLK_AHB 2
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+#define ATH79_CLK_REF 3
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-#define ATH79_CLK_END 3
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+#define ATH79_CLK_END 4
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#endif /* __DT_BINDINGS_ATH79_CLK_H */
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