openwrt-mirror/target/linux/generic/pending-6.6/720-04-net-phy-realtek-setup-aldps.patch
Aleksander Jan Bajkowski 787c1106d5 kernel: backport upstream realtek PHY patches
Changelog:
18aa36238a4d: net: phy: realtek: add interrupt support for RTL8221B
61958b33ef0b: net: phy: realtek: Add RTL8224 cable testing support
ffff5c8fc2af: net: phy: realtek: fix rtl8221b-vm-cg name
2c67301584f2: net: phy: realtek: Avoid PHYCR2 access if PHYCR2 not present
f63f21e82eca: net: phy: realtek: support for TRIGGER_NETDEV_LINK on RTL8211E and RTL8211F
a9b24b3583ae: net: phy: realtek: add error handling to rtl8211f_get_wol

Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/20650
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2025-11-15 20:43:19 +01:00

43 lines
1.4 KiB
Diff

From 9155098547fb1172d4fa536f3f6bc9d42f59d08c Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Sat, 22 Apr 2023 03:26:01 +0100
Subject: [PATCH] net: phy: realtek: setup ALDPS on RTL822x
Setup Link Down Power Saving Mode according the DTS property
just like for RTL821x 1GE PHYs.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/net/phy/realtek/realtek_main.c | 11 +++++++++++
1 file changed, 11 insertions(+)
--- a/drivers/net/phy/realtek/realtek_main.c
+++ b/drivers/net/phy/realtek/realtek_main.c
@@ -156,6 +156,10 @@
#define RTL8224_SRAM_RTCT_LEN(pair) (0x8028 + (pair) * 4)
+#define RTL8221B_PHYCR1 0xa430
+#define RTL8221B_PHYCR1_ALDPS_EN BIT(2)
+#define RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN BIT(12)
+
#define RTL8366RB_POWER_SAVE 0x15
#define RTL8366RB_POWER_SAVE_ON BIT(12)
@@ -1147,6 +1151,15 @@ static int rtl822xb_config_init(struct p
if (ret < 0)
return ret;
+ if (of_property_read_bool(phydev->mdio.dev.of_node, "realtek,aldps-enable"))
+ ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, RTL8221B_PHYCR1,
+ RTL8221B_PHYCR1_ALDPS_EN | RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN);
+ else
+ ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, RTL8221B_PHYCR1,
+ RTL8221B_PHYCR1_ALDPS_EN | RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN);
+ if (ret < 0)
+ return ret;
+
/* Disable SGMII AN */
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x7588, 0x2);
if (ret < 0)