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c6c731fe31
Add support for NXP layerscape ls1043ardb 64b/32b Dev board. LS1043a is an SoC with 4x64-bit up to 1.6 GHz ARMv8 A53 cores. ls1043ardb support features as: 2GB DDR4, 128MB NOR/512MB NAND, USB3.0, eSDHC, I2C, GPIO, PCIe/Mini-PCIe, 6x1G/1x10G network port, etc. 64b/32b ls1043ardb target is using 4.4 kernel, and rcw/u-boot/fman images from NXP QorIQ SDK release. All of 4.4 kernel patches porting from SDK release or upstream. QorIQ SDK ISOs can be downloaded from this location: http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
142 lines
3.1 KiB
Diff
142 lines
3.1 KiB
Diff
From 3970a709eb4c25e298e11cfe0ea7412bb2139197 Mon Sep 17 00:00:00 2001
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From: Alison Wang <alison.wang@nxp.com>
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Date: Fri, 8 Jul 2016 10:50:46 +0800
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Subject: [PATCH 03/70] arm64: dts: Update address-cells and reg properties of
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cpu nodes
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commit 67161e229a59faf81732892b45a9ab3bae62ea18
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[context adjustment]
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MPIDR_EL1[63:32] value is equal to 0 for the CPUs of the LS1043A and
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LS2080A SoCs. The ARM CPU binding allows #address-cells to be set to 1,
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since MPIDR_EL1[63:32] bits are not used for CPUs identification. Update
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the #address-cells and reg properties accordingly.
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Signed-off-by: Alison Wang <alison.wang@nxp.com>
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Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
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---
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 10 +++++-----
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arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 18 +++++++++---------
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2 files changed, 14 insertions(+), 14 deletions(-)
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
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@@ -51,7 +51,7 @@
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#size-cells = <2>;
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cpus {
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- #address-cells = <2>;
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+ #address-cells = <1>;
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#size-cells = <0>;
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/*
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@@ -63,28 +63,28 @@
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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- reg = <0x0 0x0>;
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+ reg = <0x0>;
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clocks = <&clockgen 1 0>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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- reg = <0x0 0x1>;
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+ reg = <0x1>;
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clocks = <&clockgen 1 0>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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- reg = <0x0 0x2>;
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+ reg = <0x2>;
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clocks = <&clockgen 1 0>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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- reg = <0x0 0x3>;
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+ reg = <0x3>;
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clocks = <&clockgen 1 0>;
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};
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};
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--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
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@@ -51,7 +51,7 @@
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#size-cells = <2>;
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cpus {
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- #address-cells = <2>;
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+ #address-cells = <1>;
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#size-cells = <0>;
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/*
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@@ -65,56 +65,56 @@
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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- reg = <0x0 0x0>;
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+ reg = <0x0>;
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clocks = <&clockgen 1 0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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- reg = <0x0 0x1>;
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+ reg = <0x1>;
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clocks = <&clockgen 1 0>;
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};
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cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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- reg = <0x0 0x100>;
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+ reg = <0x100>;
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clocks = <&clockgen 1 1>;
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};
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cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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- reg = <0x0 0x101>;
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+ reg = <0x101>;
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clocks = <&clockgen 1 1>;
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};
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cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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- reg = <0x0 0x200>;
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+ reg = <0x200>;
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clocks = <&clockgen 1 2>;
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};
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cpu@201 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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- reg = <0x0 0x201>;
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+ reg = <0x201>;
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clocks = <&clockgen 1 2>;
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};
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cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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- reg = <0x0 0x300>;
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+ reg = <0x300>;
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clocks = <&clockgen 1 3>;
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};
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cpu@301 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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- reg = <0x0 0x301>;
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+ reg = <0x301>;
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clocks = <&clockgen 1 3>;
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};
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};
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