mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2025-11-03 14:34:27 -05:00
1d5778e18d
Select many potentially useful options for the MT7988 RFB U-Boot builds. The resulting loader is intended as a development tool and intends to be generic. It does *not* have a default bootcmd set, but allows to boot pretty much everything, including EFI executables. To install this U-Boot build to the eMMC: opkg install mmc-utils partx-utils mmc bootpart enable 1 1 /dev/mmcblk0 echo 0 > /sys/block/mmcblk0boot0/force_ro dd if=*mediatek_mt7988a-rfb-nand-emmc-preloader.bin of=/dev/mmcblk0boot0 dd if=*mediatek_mt7988a-rfb-nand-emmc-gpt.bin of=/dev/mmcblk0 partx -a /dev/mmcblk0 dd if=*mediatek_mt7988a-rfb-nand-emmc-bl31-uboot.fip of=/dev/mmcblk0p3 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
576 lines
12 KiB
Diff
576 lines
12 KiB
Diff
From fd7d9124ffa6761f27747daeea599e0ab874c1fa Mon Sep 17 00:00:00 2001
|
|
From: Weijie Gao <weijie.gao@mediatek.com>
|
|
Date: Wed, 19 Jul 2023 17:17:54 +0800
|
|
Subject: [PATCH 29/29] board: mediatek: add MT7988 reference boards
|
|
|
|
This patch adds general board files based on MT7988 SoCs.
|
|
|
|
MT7988 uses one mmc controller for booting from both SD and eMMC,
|
|
and the pins of mmc controller booting from SD are also shared with
|
|
one of spi controllers.
|
|
So two configs are need for these boot types:
|
|
|
|
1. mt7988_rfb_defconfig - SPI-NOR, SPI-NAND and eMMC
|
|
2. mt7988_sd_rfb_defconfig - SPI-NAND and SD
|
|
|
|
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
|
|
---
|
|
arch/arm/dts/Makefile | 2 +
|
|
arch/arm/dts/mt7988-rfb.dts | 182 +++++++++++++++++++++++++++++
|
|
arch/arm/dts/mt7988-sd-rfb.dts | 134 +++++++++++++++++++++
|
|
board/mediatek/mt7988/MAINTAINERS | 7 ++
|
|
board/mediatek/mt7988/Makefile | 3 +
|
|
board/mediatek/mt7988/mt7988_rfb.c | 10 ++
|
|
configs/mt7988_rfb_defconfig | 83 +++++++++++++
|
|
configs/mt7988_sd_rfb_defconfig | 71 +++++++++++
|
|
include/configs/mt7988.h | 14 +++
|
|
9 files changed, 506 insertions(+)
|
|
create mode 100644 arch/arm/dts/mt7988-rfb.dts
|
|
create mode 100644 arch/arm/dts/mt7988-sd-rfb.dts
|
|
create mode 100644 board/mediatek/mt7988/MAINTAINERS
|
|
create mode 100644 board/mediatek/mt7988/Makefile
|
|
create mode 100644 board/mediatek/mt7988/mt7988_rfb.c
|
|
create mode 100644 configs/mt7988_rfb_defconfig
|
|
create mode 100644 configs/mt7988_sd_rfb_defconfig
|
|
create mode 100644 include/configs/mt7988.h
|
|
|
|
--- a/arch/arm/dts/Makefile
|
|
+++ b/arch/arm/dts/Makefile
|
|
@@ -1319,6 +1319,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
|
|
mt7986b-sd-rfb.dtb \
|
|
mt7986a-emmc-rfb.dtb \
|
|
mt7986b-emmc-rfb.dtb \
|
|
+ mt7988-rfb.dtb \
|
|
+ mt7988-sd-rfb.dtb \
|
|
mt8183-pumpkin.dtb \
|
|
mt8512-bm1-emmc.dtb \
|
|
mt8516-pumpkin.dtb \
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/mt7988-rfb.dts
|
|
@@ -0,0 +1,182 @@
|
|
+// SPDX-License-Identifier: GPL-2.0
|
|
+/*
|
|
+ * Copyright (c) 2022 MediaTek Inc.
|
|
+ * Author: Sam Shih <sam.shih@mediatek.com>
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+#include "mt7988.dtsi"
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
+
|
|
+/ {
|
|
+ model = "mt7988-rfb";
|
|
+ compatible = "mediatek,mt7988-rfb";
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = &uart0;
|
|
+ };
|
|
+
|
|
+ memory@40000000 {
|
|
+ device_type = "memory";
|
|
+ reg = <0 0x40000000 0 0x10000000>;
|
|
+ };
|
|
+
|
|
+ reg_3p3v: regulator-3p3v {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "fixed-3.3V";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+
|
|
+ reg_1p8v: regulator-1p8v {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "fixed-1.8V";
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+};
|
|
+
|
|
+&uart0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&i2c1 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c1_pins>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+ð {
|
|
+ status = "okay";
|
|
+ mediatek,gmac-id = <0>;
|
|
+ phy-mode = "usxgmii";
|
|
+ mediatek,switch = "mt7988";
|
|
+
|
|
+ fixed-link {
|
|
+ speed = <1000>;
|
|
+ full-duplex;
|
|
+ pause;
|
|
+ };
|
|
+};
|
|
+
|
|
+&pinctrl {
|
|
+ i2c1_pins: i2c1-pins {
|
|
+ mux {
|
|
+ function = "i2c";
|
|
+ groups = "i2c1_0";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm_pins: pwm-pins {
|
|
+ mux {
|
|
+ function = "pwm";
|
|
+ groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
|
|
+ "pwm5", "pwm6", "pwm7";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spi0_pins: spi0-pins {
|
|
+ mux {
|
|
+ function = "spi";
|
|
+ groups = "spi0", "spi0_wp_hold";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spi2_pins: spi2-pins {
|
|
+ mux {
|
|
+ function = "spi";
|
|
+ groups = "spi2", "spi2_wp_hold";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ mmc0_pins_default: mmc0default {
|
|
+ mux {
|
|
+ function = "flash";
|
|
+ groups = "emmc_51";
|
|
+ };
|
|
+
|
|
+ conf-cmd-dat {
|
|
+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
|
|
+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
|
|
+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
|
|
+ input-enable;
|
|
+ };
|
|
+
|
|
+ conf-clk {
|
|
+ pins = "EMMC_CK";
|
|
+ };
|
|
+
|
|
+ conf-dsl {
|
|
+ pins = "EMMC_DSL";
|
|
+ };
|
|
+
|
|
+ conf-rst {
|
|
+ pins = "EMMC_RSTB";
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&pwm {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pwm_pins>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&spi0 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spi0_pins>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "okay";
|
|
+ must_tx;
|
|
+ enhance_timing;
|
|
+ dma_ext;
|
|
+ ipm_design;
|
|
+ support_quad;
|
|
+ tick_dly = <2>;
|
|
+ sample_sel = <0>;
|
|
+
|
|
+ spi_nand@0 {
|
|
+ compatible = "spi-nand";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <52000000>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&spi2 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spi2_pins>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "okay";
|
|
+ must_tx;
|
|
+ enhance_timing;
|
|
+ dma_ext;
|
|
+ ipm_design;
|
|
+ support_quad;
|
|
+ tick_dly = <2>;
|
|
+ sample_sel = <0>;
|
|
+
|
|
+ spi_nor@0 {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <52000000>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&mmc0 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&mmc0_pins_default>;
|
|
+ max-frequency = <52000000>;
|
|
+ bus-width = <8>;
|
|
+ cap-mmc-highspeed;
|
|
+ cap-mmc-hw-reset;
|
|
+ vmmc-supply = <®_3p3v>;
|
|
+ vqmmc-supply = <®_1p8v>;
|
|
+ non-removable;
|
|
+ status = "okay";
|
|
+};
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/mt7988-sd-rfb.dts
|
|
@@ -0,0 +1,134 @@
|
|
+// SPDX-License-Identifier: GPL-2.0
|
|
+/*
|
|
+ * Copyright (c) 2022 MediaTek Inc.
|
|
+ * Author: Sam Shih <sam.shih@mediatek.com>
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+#include "mt7988.dtsi"
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
+
|
|
+/ {
|
|
+ model = "mt7988-rfb";
|
|
+ compatible = "mediatek,mt7988-rfb", "mediatek,mt7988-sd-rfb";
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = &uart0;
|
|
+ };
|
|
+
|
|
+ memory@40000000 {
|
|
+ device_type = "memory";
|
|
+ reg = <0 0x40000000 0 0x10000000>;
|
|
+ };
|
|
+
|
|
+ reg_3p3v: regulator-3p3v {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "fixed-3.3V";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+};
|
|
+
|
|
+&uart0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&i2c1 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c1_pins>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+ð {
|
|
+ status = "okay";
|
|
+ mediatek,gmac-id = <0>;
|
|
+ phy-mode = "usxgmii";
|
|
+ mediatek,switch = "mt7988";
|
|
+
|
|
+ fixed-link {
|
|
+ speed = <1000>;
|
|
+ full-duplex;
|
|
+ pause;
|
|
+ };
|
|
+};
|
|
+
|
|
+&pinctrl {
|
|
+ i2c1_pins: i2c1-pins {
|
|
+ mux {
|
|
+ function = "i2c";
|
|
+ groups = "i2c1_0";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm_pins: pwm-pins {
|
|
+ mux {
|
|
+ function = "pwm";
|
|
+ groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
|
|
+ "pwm5", "pwm6", "pwm7";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spi0_pins: spi0-pins {
|
|
+ mux {
|
|
+ function = "spi";
|
|
+ groups = "spi0", "spi0_wp_hold";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ mmc1_pins_default: mmc1default {
|
|
+ mux {
|
|
+ function = "flash";
|
|
+ groups = "emmc_45";
|
|
+ };
|
|
+
|
|
+ conf-cmd-dat {
|
|
+ pins = "SPI2_CSB", "SPI2_MISO", "SPI2_MOSI",
|
|
+ "SPI2_CLK", "SPI2_HOLD";
|
|
+ input-enable;
|
|
+ };
|
|
+
|
|
+ conf-clk {
|
|
+ pins = "SPI2_WP";
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&pwm {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pwm_pins>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&spi0 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spi0_pins>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "okay";
|
|
+ must_tx;
|
|
+ enhance_timing;
|
|
+ dma_ext;
|
|
+ ipm_design;
|
|
+ support_quad;
|
|
+ tick_dly = <2>;
|
|
+ sample_sel = <0>;
|
|
+
|
|
+ spi_nand@0 {
|
|
+ compatible = "spi-nand";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <52000000>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&mmc0 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&mmc1_pins_default>;
|
|
+ max-frequency = <52000000>;
|
|
+ bus-width = <4>;
|
|
+ cap-sd-highspeed;
|
|
+ vmmc-supply = <®_3p3v>;
|
|
+ vqmmc-supply = <®_3p3v>;
|
|
+ status = "okay";
|
|
+};
|
|
--- /dev/null
|
|
+++ b/board/mediatek/mt7988/MAINTAINERS
|
|
@@ -0,0 +1,7 @@
|
|
+MT7988
|
|
+M: Sam Shih <sam.shih@mediatek.com>
|
|
+S: Maintained
|
|
+F: board/mediatek/mt7988
|
|
+F: include/configs/mt7988.h
|
|
+F: configs/mt7988_rfb_defconfig
|
|
+F: configs/mt7988_sd_rfb_defconfig
|
|
--- /dev/null
|
|
+++ b/board/mediatek/mt7988/Makefile
|
|
@@ -0,0 +1,3 @@
|
|
+# SPDX-License-Identifier: GPL-2.0
|
|
+
|
|
+obj-y += mt7988_rfb.o
|
|
--- /dev/null
|
|
+++ b/board/mediatek/mt7988/mt7988_rfb.c
|
|
@@ -0,0 +1,10 @@
|
|
+// SPDX-License-Identifier: GPL-2.0
|
|
+/*
|
|
+ * Copyright (C) 2022 MediaTek Inc.
|
|
+ * Author: Sam Shih <sam.shih@mediatek.com>
|
|
+ */
|
|
+
|
|
+int board_init(void)
|
|
+{
|
|
+ return 0;
|
|
+}
|
|
--- /dev/null
|
|
+++ b/configs/mt7988_rfb_defconfig
|
|
@@ -0,0 +1,83 @@
|
|
+CONFIG_ARM=y
|
|
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
|
|
+CONFIG_POSITION_INDEPENDENT=y
|
|
+CONFIG_ARCH_MEDIATEK=y
|
|
+CONFIG_TEXT_BASE=0x41e00000
|
|
+CONFIG_SYS_MALLOC_F_LEN=0x4000
|
|
+CONFIG_NR_DRAM_BANKS=1
|
|
+CONFIG_DEFAULT_DEVICE_TREE="mt7988-rfb"
|
|
+CONFIG_SYS_PROMPT="MT7988> "
|
|
+CONFIG_TARGET_MT7988=y
|
|
+CONFIG_DEBUG_UART_BASE=0x11000000
|
|
+CONFIG_DEBUG_UART_CLOCK=40000000
|
|
+CONFIG_SYS_LOAD_ADDR=0x50000000
|
|
+CONFIG_DEBUG_UART=y
|
|
+# CONFIG_AUTOBOOT is not set
|
|
+CONFIG_DEFAULT_FDT_FILE="mt7988-rfb"
|
|
+CONFIG_LOGLEVEL=7
|
|
+CONFIG_LOG=y
|
|
+CONFIG_SYS_CBSIZE=512
|
|
+CONFIG_SYS_PBSIZE=1049
|
|
+# CONFIG_BOOTM_NETBSD is not set
|
|
+# CONFIG_BOOTM_PLAN9 is not set
|
|
+# CONFIG_BOOTM_RTEMS is not set
|
|
+# CONFIG_BOOTM_VXWORKS is not set
|
|
+# CONFIG_CMD_ELF is not set
|
|
+CONFIG_CMD_CLK=y
|
|
+CONFIG_CMD_DM=y
|
|
+CONFIG_CMD_GPIO=y
|
|
+CONFIG_CMD_PWM=y
|
|
+CONFIG_CMD_MMC=y
|
|
+CONFIG_CMD_MTD=y
|
|
+CONFIG_CMD_PING=y
|
|
+CONFIG_CMD_SMC=y
|
|
+CONFIG_DOS_PARTITION=y
|
|
+CONFIG_EFI_PARTITION=y
|
|
+CONFIG_PARTITION_TYPE_GUID=y
|
|
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
|
+CONFIG_NET_RANDOM_ETHADDR=y
|
|
+CONFIG_USE_IPADDR=y
|
|
+CONFIG_IPADDR="192.168.1.1"
|
|
+CONFIG_USE_NETMASK=y
|
|
+CONFIG_NETMASK="255.255.255.0"
|
|
+CONFIG_USE_SERVERIP=y
|
|
+CONFIG_SERVERIP="192.168.1.2"
|
|
+CONFIG_PROT_TCP=y
|
|
+CONFIG_REGMAP=y
|
|
+CONFIG_SYSCON=y
|
|
+CONFIG_CLK=y
|
|
+CONFIG_MMC_HS200_SUPPORT=y
|
|
+CONFIG_MMC_MTK=y
|
|
+CONFIG_MTD=y
|
|
+CONFIG_DM_MTD=y
|
|
+CONFIG_MTD_SPI_NAND=y
|
|
+CONFIG_DM_SPI_FLASH=y
|
|
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
|
+CONFIG_SPI_FLASH_EON=y
|
|
+CONFIG_SPI_FLASH_GIGADEVICE=y
|
|
+CONFIG_SPI_FLASH_ISSI=y
|
|
+CONFIG_SPI_FLASH_MACRONIX=y
|
|
+CONFIG_SPI_FLASH_SPANSION=y
|
|
+CONFIG_SPI_FLASH_STMICRO=y
|
|
+CONFIG_SPI_FLASH_WINBOND=y
|
|
+CONFIG_SPI_FLASH_XMC=y
|
|
+CONFIG_SPI_FLASH_XTX=y
|
|
+CONFIG_SPI_FLASH_MTD=y
|
|
+CONFIG_PHY_FIXED=y
|
|
+CONFIG_MEDIATEK_ETH=y
|
|
+CONFIG_PINCTRL=y
|
|
+CONFIG_PINCONF=y
|
|
+CONFIG_PINCTRL_MT7988=y
|
|
+CONFIG_POWER_DOMAIN=y
|
|
+CONFIG_MTK_POWER_DOMAIN=y
|
|
+CONFIG_DM_PWM=y
|
|
+CONFIG_PWM_MTK=y
|
|
+CONFIG_RAM=y
|
|
+CONFIG_DM_SERIAL=y
|
|
+CONFIG_MTK_SERIAL=y
|
|
+CONFIG_SPI=y
|
|
+CONFIG_DM_SPI=y
|
|
+CONFIG_MTK_SPIM=y
|
|
+CONFIG_LZO=y
|
|
+CONFIG_HEXDUMP=y
|
|
+# CONFIG_EFI_LOADER is not set
|
|
--- /dev/null
|
|
+++ b/configs/mt7988_sd_rfb_defconfig
|
|
@@ -0,0 +1,71 @@
|
|
+CONFIG_ARM=y
|
|
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
|
|
+CONFIG_POSITION_INDEPENDENT=y
|
|
+CONFIG_ARCH_MEDIATEK=y
|
|
+CONFIG_TEXT_BASE=0x41e00000
|
|
+CONFIG_SYS_MALLOC_F_LEN=0x4000
|
|
+CONFIG_NR_DRAM_BANKS=1
|
|
+CONFIG_DEFAULT_DEVICE_TREE="mt7988-sd-rfb"
|
|
+CONFIG_SYS_PROMPT="MT7988> "
|
|
+CONFIG_TARGET_MT7988=y
|
|
+CONFIG_DEBUG_UART_BASE=0x11000000
|
|
+CONFIG_DEBUG_UART_CLOCK=40000000
|
|
+CONFIG_SYS_LOAD_ADDR=0x50000000
|
|
+CONFIG_DEBUG_UART=y
|
|
+# CONFIG_AUTOBOOT is not set
|
|
+CONFIG_DEFAULT_FDT_FILE="mt7988-sd-rfb"
|
|
+CONFIG_LOGLEVEL=7
|
|
+CONFIG_LOG=y
|
|
+CONFIG_SYS_CBSIZE=512
|
|
+CONFIG_SYS_PBSIZE=1049
|
|
+# CONFIG_BOOTM_NETBSD is not set
|
|
+# CONFIG_BOOTM_PLAN9 is not set
|
|
+# CONFIG_BOOTM_RTEMS is not set
|
|
+# CONFIG_BOOTM_VXWORKS is not set
|
|
+# CONFIG_CMD_ELF is not set
|
|
+CONFIG_CMD_CLK=y
|
|
+CONFIG_CMD_DM=y
|
|
+CONFIG_CMD_GPIO=y
|
|
+CONFIG_CMD_PWM=y
|
|
+CONFIG_CMD_MMC=y
|
|
+CONFIG_CMD_MTD=y
|
|
+CONFIG_CMD_PING=y
|
|
+CONFIG_CMD_SMC=y
|
|
+CONFIG_DOS_PARTITION=y
|
|
+CONFIG_EFI_PARTITION=y
|
|
+CONFIG_PARTITION_TYPE_GUID=y
|
|
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
|
+CONFIG_NET_RANDOM_ETHADDR=y
|
|
+CONFIG_USE_IPADDR=y
|
|
+CONFIG_IPADDR="192.168.1.1"
|
|
+CONFIG_USE_NETMASK=y
|
|
+CONFIG_NETMASK="255.255.255.0"
|
|
+CONFIG_USE_SERVERIP=y
|
|
+CONFIG_SERVERIP="192.168.1.2"
|
|
+CONFIG_PROT_TCP=y
|
|
+CONFIG_REGMAP=y
|
|
+CONFIG_SYSCON=y
|
|
+CONFIG_CLK=y
|
|
+CONFIG_MMC_HS200_SUPPORT=y
|
|
+CONFIG_MMC_MTK=y
|
|
+CONFIG_MTD=y
|
|
+CONFIG_DM_MTD=y
|
|
+CONFIG_MTD_SPI_NAND=y
|
|
+CONFIG_PHY_FIXED=y
|
|
+CONFIG_MEDIATEK_ETH=y
|
|
+CONFIG_PINCTRL=y
|
|
+CONFIG_PINCONF=y
|
|
+CONFIG_PINCTRL_MT7988=y
|
|
+CONFIG_POWER_DOMAIN=y
|
|
+CONFIG_MTK_POWER_DOMAIN=y
|
|
+CONFIG_DM_PWM=y
|
|
+CONFIG_PWM_MTK=y
|
|
+CONFIG_RAM=y
|
|
+CONFIG_DM_SERIAL=y
|
|
+CONFIG_MTK_SERIAL=y
|
|
+CONFIG_SPI=y
|
|
+CONFIG_DM_SPI=y
|
|
+CONFIG_MTK_SPIM=y
|
|
+CONFIG_LZO=y
|
|
+CONFIG_HEXDUMP=y
|
|
+# CONFIG_EFI_LOADER is not set
|
|
--- /dev/null
|
|
+++ b/include/configs/mt7988.h
|
|
@@ -0,0 +1,14 @@
|
|
+/* SPDX-License-Identifier: GPL-2.0 */
|
|
+/*
|
|
+ * Configuration for MediaTek MT7988 SoC
|
|
+ *
|
|
+ * Copyright (C) 2022 MediaTek Inc.
|
|
+ * Author: Sam Shih <sam.shih@mediatek.com>
|
|
+ */
|
|
+
|
|
+#ifndef __MT7988_H
|
|
+#define __MT7988_H
|
|
+
|
|
+#define CFG_MAX_MEM_MAPPED 0xC0000000
|
|
+
|
|
+#endif
|