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git://git.openwrt.org/openwrt/openwrt.git
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68d9cb8214
Run tested: ath79, ipq40xx Build tested: ath79, ipq40xx Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
61 lines
2.1 KiB
Diff
61 lines
2.1 KiB
Diff
From c89d85a39df353290ea7af84a32d5ca692a3c27a Mon Sep 17 00:00:00 2001
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From: Fugang Duan <fugang.duan@nxp.com>
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Date: Sat, 2 Nov 2019 15:51:40 +0800
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Subject: [PATCH] PCI: dwc: Use interrupt disabling instead of masking
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commit 830920e065e9("PCI: dwc: Use interrupt masking instead
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of disabling") break i.MX platform PCIe suspend/resume when
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MSI enabled.
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Revert the commit to keep orinigal method that using interrupt
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disabling instead of masking.
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Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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---
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drivers/pci/controller/dwc/pcie-designware-host.c | 19 +++++++------------
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1 file changed, 7 insertions(+), 12 deletions(-)
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--- a/drivers/pci/controller/dwc/pcie-designware-host.c
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+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
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@@ -157,8 +157,8 @@ static void dw_pci_bottom_mask(struct ir
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bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
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pp->irq_mask[ctrl] |= BIT(bit);
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- dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
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- pp->irq_mask[ctrl]);
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+ dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4,
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+ ~pp->irq_mask[ctrl]);
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raw_spin_unlock_irqrestore(&pp->lock, flags);
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}
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@@ -176,8 +176,8 @@ static void dw_pci_bottom_unmask(struct
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bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
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pp->irq_mask[ctrl] &= ~BIT(bit);
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- dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
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- pp->irq_mask[ctrl]);
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+ dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4,
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+ ~pp->irq_mask[ctrl]);
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raw_spin_unlock_irqrestore(&pp->lock, flags);
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}
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@@ -659,15 +659,10 @@ void dw_pcie_setup_rc(struct pcie_port *
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num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
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/* Initialize IRQ Status array */
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- for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
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- pp->irq_mask[ctrl] = ~0;
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- dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK +
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+ for (ctrl = 0; ctrl < num_ctrls; ctrl++)
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+ dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE +
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(ctrl * MSI_REG_CTRL_BLOCK_SIZE),
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- 4, pp->irq_mask[ctrl]);
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- dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE +
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- (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
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- 4, ~0);
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- }
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+ 4, &pp->irq_mask[ctrl]);
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}
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/* Setup RC BARs */
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