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a282a04538
All modifications made by update_kernel.sh run in a fresh clone without any existing toolchains. Build system: x86_64 Build-tested: ipq806x/R7800, ath79/generic, bcm27xx/bcm2711 Run-tested: ipq806x/R7800 No dmesg regressions, everything functional Signed-off-by: John Audia <graysky@archlinux.us>
62 lines
2.4 KiB
Diff
62 lines
2.4 KiB
Diff
From e2b0ebb44e91e3492f26d21218fb7ea5e14190ec Mon Sep 17 00:00:00 2001
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From: Haiying Wang <Haiying.Wang@nxp.com>
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Date: Thu, 20 Apr 2017 11:54:22 -0400
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Subject: [PATCH] soc: fsl: dpio: change CENA regs to be cacheable
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Change cache enabled regsiter accessed to be cacheable
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plus non-shareable to meet the performance requirement.
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QMan's CENA region contains registers and structures that
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are 64byte in size and are inteneded to be accessed using a
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single 64 byte bus transaction, therefore this portal
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memory should be configured as cache-enabled. Also because
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the write allocate stash transcations of QBMan should be
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issued as cachable and non-coherent(non-sharable), we
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need to configure this region to be non-shareable.
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Signed-off-by: Haiying Wang <Haiying.Wang@nxp.com>
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---
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drivers/soc/fsl/dpio/dpio-driver.c | 17 ++++++++++-------
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1 file changed, 10 insertions(+), 7 deletions(-)
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--- a/drivers/soc/fsl/dpio/dpio-driver.c
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+++ b/drivers/soc/fsl/dpio/dpio-driver.c
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@@ -27,6 +27,11 @@ MODULE_LICENSE("Dual BSD/GPL");
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MODULE_AUTHOR("Freescale Semiconductor, Inc");
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MODULE_DESCRIPTION("DPIO Driver");
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+#define PROT_NORMAL_NS (PTE_TYPE_PAGE | PTE_AF | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
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+
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+#define ioremap_cache_ns(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NS))
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+
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+
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struct dpio_priv {
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struct dpaa2_io *io;
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};
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@@ -197,13 +202,11 @@ static int dpaa2_dpio_probe(struct fsl_m
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if (dpio_dev->obj_desc.region_count < 3) {
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/* No support for DDR backed portals, use classic mapping */
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/*
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- * Set the CENA regs to be the cache inhibited area of the
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- * portal to avoid coherency issues if a user migrates to
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- * another core.
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+ * Set the CENA regs to be the cache enabled area of the portal to
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+ * achieve the best performance.
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*/
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- desc.regs_cena = devm_memremap(dev, dpio_dev->regions[1].start,
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- resource_size(&dpio_dev->regions[1]),
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- MEMREMAP_WC);
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+ desc.regs_cena = ioremap_cache_ns(dpio_dev->regions[0].start,
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+ resource_size(&dpio_dev->regions[0]));
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} else {
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desc.regs_cena = devm_memremap(dev, dpio_dev->regions[2].start,
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resource_size(&dpio_dev->regions[2]),
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@@ -211,7 +214,7 @@ static int dpaa2_dpio_probe(struct fsl_m
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}
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if (IS_ERR(desc.regs_cena)) {
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- dev_err(dev, "devm_memremap failed\n");
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+ dev_err(dev, "ioremap_cache_ns failed\n");
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err = PTR_ERR(desc.regs_cena);
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goto err_allocate_irqs;
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}
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