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f2f42a54e8
The qca8k patch series brings the numbering to 799. This patch renames 7xx patches to create space for more backports to be added. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> [rename 729->719] Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
94 lines
2.5 KiB
Diff
94 lines
2.5 KiB
Diff
From 0c994a28e7518f098c84a3049cb2915780db873a Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Fri, 14 May 2021 23:00:11 +0200
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Subject: [PATCH] devicetree: bindings: dsa: qca8k: Document internal mdio
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definition
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Document new way of declare mapping of internal PHY to port.
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The new implementation directly declare the PHY connected to the port
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by adding a node in the switch node. The driver detect this and register
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an internal mdiobus using the mapping defined in the mdio node.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Reviewed-by: Rob Herring <robh@kernel.org>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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.../devicetree/bindings/net/dsa/qca8k.txt | 39 +++++++++++++++++++
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1 file changed, 39 insertions(+)
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--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt
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+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
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@@ -21,6 +21,10 @@ described in dsa/dsa.txt. If the QCA8K s
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mdio-bus each subnode describing a port needs to have a valid phandle
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referencing the internal PHY it is connected to. This is because there's no
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N:N mapping of port and PHY id.
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+To declare the internal mdio-bus configuration, declare a mdio node in the
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+switch node and declare the phandle for the port referencing the internal
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+PHY is connected to. In this config a internal mdio-bus is registered and
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+the mdio MASTER is used as communication.
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Don't use mixed external and internal mdio-bus configurations, as this is
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not supported by the hardware.
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@@ -150,26 +154,61 @@ for the internal master mdio-bus configu
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port@1 {
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reg = <1>;
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label = "lan1";
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+ phy-mode = "internal";
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+ phy-handle = <&phy_port1>;
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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+ phy-mode = "internal";
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+ phy-handle = <&phy_port2>;
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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+ phy-mode = "internal";
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+ phy-handle = <&phy_port3>;
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};
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port@4 {
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reg = <4>;
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label = "lan4";
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+ phy-mode = "internal";
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+ phy-handle = <&phy_port4>;
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};
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port@5 {
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reg = <5>;
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label = "wan";
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+ phy-mode = "internal";
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+ phy-handle = <&phy_port5>;
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+ };
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+ };
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+
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+ mdio {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ phy_port1: phy@0 {
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+ reg = <0>;
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+ };
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+
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+ phy_port2: phy@1 {
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+ reg = <1>;
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+ };
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+
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+ phy_port3: phy@2 {
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+ reg = <2>;
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+ };
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+
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+ phy_port4: phy@3 {
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+ reg = <3>;
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+ };
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+
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+ phy_port5: phy@4 {
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+ reg = <4>;
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};
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};
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};
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