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ec6293febc
Ran update_kernel.sh in a fresh clone without any existing toolchains.
Manually rebased:
pending-5.4/611-netfilter_match_bypass_default_table.patch
The upstream change affecting this patch is the revert of an earlier
kernel commit. Therefore, we just revert our corresponding changes
in [1].
Build system: x86_64
Build-tested: ipq806x/R7800
[1] 9b1b89229f ("kernel: bump 5.4 to 5.4.86")
Signed-off-by: John Audia <graysky@archlinux.us>
[adjust manually rebased patch, add explanation]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
153 lines
4.8 KiB
Diff
153 lines
4.8 KiB
Diff
From a9349f08ec6c1251d41ef167d27a15cc39bc5b97 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
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Date: Fri, 12 Mar 2021 11:41:08 +0100
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Subject: [PATCH] net: dsa: bcm_sf2: setup BCM4908 internal crossbar
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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On some SoCs (e.g. BCM4908, BCM631[345]8) SF2 has an integrated
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crossbar. It allows connecting its selected external ports to internal
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ports. It's used by vendors to handle custom Ethernet setups.
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BCM4908 has following 3x2 crossbar. On Asus GT-AC5300 rgmii is used for
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connecting external BCM53134S switch. GPHY4 is usually used for WAN
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port. More fancy devices use SerDes for 2.5 Gbps Ethernet.
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┌──────────┐
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SerDes ─── 0 ─┤ │
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│ 3x2 ├─ 0 ─── switch port 7
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GPHY4 ─── 1 ─┤ │
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│ crossbar ├─ 1 ─── runner (accelerator)
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rgmii ─── 2 ─┤ │
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└──────────┘
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Use setup data based on DT info to configure BCM4908's switch port 7.
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Right now only GPHY and rgmii variants are supported. Handling SerDes
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can be implemented later.
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Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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Acked-by: Florian Fainelli <f.fainelli@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/bcm_sf2.c | 45 ++++++++++++++++++++++++++++++++++
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drivers/net/dsa/bcm_sf2.h | 1 +
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drivers/net/dsa/bcm_sf2_regs.h | 7 ++++++
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3 files changed, 53 insertions(+)
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--- a/drivers/net/dsa/bcm_sf2.c
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+++ b/drivers/net/dsa/bcm_sf2.c
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@@ -369,6 +369,44 @@ static int bcm_sf2_sw_rst(struct bcm_sf2
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return 0;
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}
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+static void bcm_sf2_crossbar_setup(struct bcm_sf2_priv *priv)
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+{
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+ struct device *dev = priv->dev->ds->dev;
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+ int shift;
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+ u32 mask;
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+ u32 reg;
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+ int i;
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+
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+ mask = BIT(priv->num_crossbar_int_ports) - 1;
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+
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+ reg = reg_readl(priv, REG_CROSSBAR);
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+ switch (priv->type) {
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+ case BCM4908_DEVICE_ID:
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+ shift = CROSSBAR_BCM4908_INT_P7 * priv->num_crossbar_int_ports;
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+ reg &= ~(mask << shift);
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+ if (0) /* FIXME */
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+ reg |= CROSSBAR_BCM4908_EXT_SERDES << shift;
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+ else if (priv->int_phy_mask & BIT(7))
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+ reg |= CROSSBAR_BCM4908_EXT_GPHY4 << shift;
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+ else if (phy_interface_mode_is_rgmii(priv->port_sts[7].mode))
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+ reg |= CROSSBAR_BCM4908_EXT_RGMII << shift;
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+ else if (WARN(1, "Invalid port mode\n"))
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+ return;
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+ break;
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+ default:
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+ return;
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+ }
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+ reg_writel(priv, reg, REG_CROSSBAR);
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+
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+ reg = reg_readl(priv, REG_CROSSBAR);
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+ for (i = 0; i < priv->num_crossbar_int_ports; i++) {
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+ shift = i * priv->num_crossbar_int_ports;
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+
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+ dev_dbg(dev, "crossbar int port #%d - ext port #%d\n", i,
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+ (reg >> shift) & mask);
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+ }
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+}
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+
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static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
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{
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intrl2_0_mask_set(priv, 0xffffffff);
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@@ -734,6 +772,8 @@ static int bcm_sf2_sw_resume(struct dsa_
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return ret;
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}
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+ bcm_sf2_crossbar_setup(priv);
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+
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ret = bcm_sf2_cfp_resume(ds);
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if (ret)
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return ret;
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@@ -996,6 +1036,7 @@ struct bcm_sf2_of_data {
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const u16 *reg_offsets;
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unsigned int core_reg_align;
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unsigned int num_cfp_rules;
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+ unsigned int num_crossbar_int_ports;
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};
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static const u16 bcm_sf2_4908_reg_offsets[] = {
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@@ -1020,6 +1061,7 @@ static const struct bcm_sf2_of_data bcm_
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.core_reg_align = 0,
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.reg_offsets = bcm_sf2_4908_reg_offsets,
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.num_cfp_rules = 0, /* FIXME */
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+ .num_crossbar_int_ports = 2,
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};
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/* Register offsets for the SWITCH_REG_* block */
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@@ -1130,6 +1172,7 @@ static int bcm_sf2_sw_probe(struct platf
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priv->reg_offsets = data->reg_offsets;
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priv->core_reg_align = data->core_reg_align;
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priv->num_cfp_rules = data->num_cfp_rules;
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+ priv->num_crossbar_int_ports = data->num_crossbar_int_ports;
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/* Auto-detection using standard registers will not work, so
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* provide an indication of what kind of device we are for
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@@ -1184,6 +1227,8 @@ static int bcm_sf2_sw_probe(struct platf
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return ret;
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}
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+ bcm_sf2_crossbar_setup(priv);
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+
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bcm_sf2_gphy_enable_set(priv->dev->ds, true);
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ret = bcm_sf2_mdio_register(ds);
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--- a/drivers/net/dsa/bcm_sf2.h
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+++ b/drivers/net/dsa/bcm_sf2.h
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@@ -70,6 +70,7 @@ struct bcm_sf2_priv {
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const u16 *reg_offsets;
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unsigned int core_reg_align;
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unsigned int num_cfp_rules;
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+ unsigned int num_crossbar_int_ports;
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/* spinlock protecting access to the indirect registers */
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spinlock_t indir_lock;
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--- a/drivers/net/dsa/bcm_sf2_regs.h
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+++ b/drivers/net/dsa/bcm_sf2_regs.h
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@@ -48,6 +48,13 @@ enum bcm_sf2_reg_offs {
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#define PHY_PHYAD_SHIFT 8
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#define PHY_PHYAD_MASK 0x1F
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+/* Relative to REG_CROSSBAR */
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+#define CROSSBAR_BCM4908_INT_P7 0
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+#define CROSSBAR_BCM4908_INT_RUNNER 1
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+#define CROSSBAR_BCM4908_EXT_SERDES 0
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+#define CROSSBAR_BCM4908_EXT_GPHY4 1
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+#define CROSSBAR_BCM4908_EXT_RGMII 2
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+
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#define REG_RGMII_CNTRL_P(x) (REG_RGMII_0_CNTRL + (x))
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/* Relative to REG_RGMII_CNTRL */
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