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ca4469045f
Replace downstream RealTek PHY patches with backported ones. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
219 lines
6.5 KiB
Diff
219 lines
6.5 KiB
Diff
From ad5ce743a6b0329f642d80be50ef7b534e908fba Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
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Date: Tue, 9 Apr 2024 09:30:13 +0200
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Subject: [PATCH] net: phy: realtek: Add driver instances for rtl8221b via
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Clause 45
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Collected from several commits in [PATCH net-next]
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"Realtek RTL822x PHY rework to c45 and SerDes interface switching"
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The instances are used by Clause 45 only accessible PHY's on several sfp
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modules, which are using RollBall protocol.
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Signed-off-by: Marek Behún <kabel@kernel.org>
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[ Added matching functions to differentiate C45 instances ]
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Signed-off-by: Eric Woudstra <ericwouds@gmail.com>
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Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/phy/realtek.c | 135 ++++++++++++++++++++++++++++++++++++--
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1 file changed, 131 insertions(+), 4 deletions(-)
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--- a/drivers/net/phy/realtek.c
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+++ b/drivers/net/phy/realtek.c
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@@ -64,6 +64,13 @@
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#define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02
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#define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16
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+/* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45
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+ * is set, they cannot be accessed by C45-over-C22.
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+ */
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+#define RTL822X_VND2_GBCR 0xa412
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+
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+#define RTL822X_VND2_GANLPAR 0xa414
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+
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#define RTL8366RB_POWER_SAVE 0x15
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#define RTL8366RB_POWER_SAVE_ON BIT(12)
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@@ -74,6 +81,9 @@
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#define RTL_GENERIC_PHYID 0x001cc800
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#define RTL_8211FVD_PHYID 0x001cc878
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+#define RTL_8221B_VB_CG 0x001cc849
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+#define RTL_8221B_VN_CG 0x001cc84a
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+#define RTL_8251B 0x001cc862
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MODULE_DESCRIPTION("Realtek PHY driver");
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MODULE_AUTHOR("Johnson Leung");
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@@ -839,6 +849,67 @@ static int rtl822xb_read_status(struct p
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return 0;
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}
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+static int rtl822x_c45_config_aneg(struct phy_device *phydev)
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+{
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+ bool changed = false;
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+ int ret, val;
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+
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+ if (phydev->autoneg == AUTONEG_DISABLE)
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+ return genphy_c45_pma_setup_forced(phydev);
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+
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+ ret = genphy_c45_an_config_aneg(phydev);
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+ if (ret < 0)
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+ return ret;
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+ if (ret > 0)
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+ changed = true;
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+
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+ val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
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+
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+ /* Vendor register as C45 has no standardized support for 1000BaseT */
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+ ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, RTL822X_VND2_GBCR,
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+ ADVERTISE_1000FULL, val);
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+ if (ret < 0)
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+ return ret;
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+ if (ret > 0)
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+ changed = true;
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+
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+ return genphy_c45_check_and_restart_aneg(phydev, changed);
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+}
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+
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+static int rtl822x_c45_read_status(struct phy_device *phydev)
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+{
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+ int ret, val;
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+
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+ ret = genphy_c45_read_status(phydev);
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+ if (ret < 0)
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+ return ret;
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+
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+ /* Vendor register as C45 has no standardized support for 1000BaseT */
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+ if (phydev->autoneg == AUTONEG_ENABLE) {
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+ val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
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+ RTL822X_VND2_GANLPAR);
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+ if (val < 0)
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+ return val;
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+
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+ mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
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+ }
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+
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+ return 0;
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+}
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+
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+static int rtl822xb_c45_read_status(struct phy_device *phydev)
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+{
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+ int ret;
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+
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+ ret = rtl822x_c45_read_status(phydev);
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+ if (ret < 0)
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+ return ret;
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+
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+ rtl822xb_update_interface(phydev);
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+
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+ return 0;
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+}
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+
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static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
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{
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int val;
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@@ -862,6 +933,35 @@ static int rtl8226_match_phy_device(stru
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rtlgen_supports_2_5gbps(phydev);
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}
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+static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id,
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+ bool is_c45)
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+{
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+ if (phydev->is_c45)
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+ return is_c45 && (id == phydev->c45_ids.device_ids[1]);
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+ else
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+ return !is_c45 && (id == phydev->phy_id);
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+}
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+
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+static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev)
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+{
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+ return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false);
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+}
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+
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+static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev)
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+{
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+ return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true);
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+}
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+
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+static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev)
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+{
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+ return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, false);
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+}
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+
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+static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev)
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+{
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+ return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true);
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+}
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+
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static int rtlgen_resume(struct phy_device *phydev)
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{
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int ret = genphy_resume(phydev);
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@@ -872,6 +972,15 @@ static int rtlgen_resume(struct phy_devi
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return ret;
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}
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+static int rtlgen_c45_resume(struct phy_device *phydev)
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+{
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+ int ret = genphy_c45_pma_resume(phydev);
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+
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+ msleep(20);
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+
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+ return ret;
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+}
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+
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static int rtl9000a_config_init(struct phy_device *phydev)
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{
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phydev->autoneg = AUTONEG_DISABLE;
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@@ -1143,8 +1252,8 @@ static struct phy_driver realtek_drvs[]
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.read_page = rtl821x_read_page,
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.write_page = rtl821x_write_page,
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}, {
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- PHY_ID_MATCH_EXACT(0x001cc849),
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- .name = "RTL8221B-VB-CG 2.5Gbps PHY",
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+ .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device,
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+ .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
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.get_features = rtl822x_get_features,
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.config_aneg = rtl822x_config_aneg,
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.config_init = rtl822xb_config_init,
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@@ -1155,8 +1264,17 @@ static struct phy_driver realtek_drvs[]
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.read_page = rtl821x_read_page,
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.write_page = rtl821x_write_page,
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}, {
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- PHY_ID_MATCH_EXACT(0x001cc84a),
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- .name = "RTL8221B-VM-CG 2.5Gbps PHY",
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+ .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device,
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+ .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)",
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+ .config_init = rtl822xb_config_init,
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+ .get_rate_matching = rtl822xb_get_rate_matching,
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+ .config_aneg = rtl822x_c45_config_aneg,
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+ .read_status = rtl822xb_c45_read_status,
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+ .suspend = genphy_c45_pma_suspend,
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+ .resume = rtlgen_c45_resume,
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+ }, {
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+ .match_phy_device = rtl8221b_vn_cg_c22_match_phy_device,
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+ .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)",
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.get_features = rtl822x_get_features,
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.config_aneg = rtl822x_config_aneg,
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.config_init = rtl822xb_config_init,
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@@ -1167,6 +1285,15 @@ static struct phy_driver realtek_drvs[]
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.read_page = rtl821x_read_page,
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.write_page = rtl821x_write_page,
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}, {
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+ .match_phy_device = rtl8221b_vn_cg_c45_match_phy_device,
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+ .name = "RTL8221B-VN-CG 2.5Gbps PHY (C45)",
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+ .config_init = rtl822xb_config_init,
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+ .get_rate_matching = rtl822xb_get_rate_matching,
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+ .config_aneg = rtl822x_c45_config_aneg,
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+ .read_status = rtl822xb_c45_read_status,
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+ .suspend = genphy_c45_pma_suspend,
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+ .resume = rtlgen_c45_resume,
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+ }, {
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PHY_ID_MATCH_EXACT(0x001cc862),
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.name = "RTL8251B 5Gbps PHY",
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.get_features = rtl822x_get_features,
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