mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2025-10-31 14:04:26 -04:00
9a038e7fd1
Copy config and patches from kernel 5.10 to kernel 5.15 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
128 lines
3.8 KiB
Diff
128 lines
3.8 KiB
Diff
From 6c43809bf1bee76c434e365a26546a92a5fbec14 Mon Sep 17 00:00:00 2001
|
|
From: Ansuel Smith <ansuelsmth@gmail.com>
|
|
Date: Thu, 14 Oct 2021 00:39:08 +0200
|
|
Subject: net: dsa: qca8k: add support for sgmii falling edge
|
|
|
|
Add support for this in the qca8k driver. Also add support for SGMII
|
|
rx/tx clock falling edge. This is only present for pad0, pad5 and
|
|
pad6 have these bit reserved from Documentation. Add a comment that this
|
|
is hardcoded to PAD0 as qca8327/28/34/37 have an unique sgmii line and
|
|
setting falling in port0 applies to both configuration with sgmii used
|
|
for port0 or port6.
|
|
|
|
Co-developed-by: Matthew Hagan <mnhagan88@gmail.com>
|
|
Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
|
|
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
|
|
Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
---
|
|
drivers/net/dsa/qca8k.c | 63 +++++++++++++++++++++++++++++++++++++++++++++++++
|
|
drivers/net/dsa/qca8k.h | 4 ++++
|
|
2 files changed, 67 insertions(+)
|
|
|
|
--- a/drivers/net/dsa/qca8k.c
|
|
+++ b/drivers/net/dsa/qca8k.c
|
|
@@ -978,6 +978,42 @@ qca8k_setup_mac_pwr_sel(struct qca8k_pri
|
|
}
|
|
|
|
static int
|
|
+qca8k_parse_port_config(struct qca8k_priv *priv)
|
|
+{
|
|
+ struct device_node *port_dn;
|
|
+ phy_interface_t mode;
|
|
+ struct dsa_port *dp;
|
|
+ int port, ret;
|
|
+
|
|
+ /* We have 2 CPU port. Check them */
|
|
+ for (port = 0; port < QCA8K_NUM_PORTS; port++) {
|
|
+ /* Skip every other port */
|
|
+ if (port != 0 && port != 6)
|
|
+ continue;
|
|
+
|
|
+ dp = dsa_to_port(priv->ds, port);
|
|
+ port_dn = dp->dn;
|
|
+
|
|
+ if (!of_device_is_available(port_dn))
|
|
+ continue;
|
|
+
|
|
+ ret = of_get_phy_mode(port_dn, &mode);
|
|
+ if (ret)
|
|
+ continue;
|
|
+
|
|
+ if (mode == PHY_INTERFACE_MODE_SGMII) {
|
|
+ if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge"))
|
|
+ priv->sgmii_tx_clk_falling_edge = true;
|
|
+
|
|
+ if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge"))
|
|
+ priv->sgmii_rx_clk_falling_edge = true;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int
|
|
qca8k_setup(struct dsa_switch *ds)
|
|
{
|
|
struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
|
|
@@ -990,6 +1026,11 @@ qca8k_setup(struct dsa_switch *ds)
|
|
return -EINVAL;
|
|
}
|
|
|
|
+ /* Parse CPU port config to be later used in phy_link mac_config */
|
|
+ ret = qca8k_parse_port_config(priv);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+
|
|
mutex_init(&priv->reg_mutex);
|
|
|
|
/* Start by setting up the register mapping */
|
|
@@ -1274,6 +1315,28 @@ qca8k_phylink_mac_config(struct dsa_swit
|
|
}
|
|
|
|
qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
|
|
+
|
|
+ /* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and
|
|
+ * falling edge is set writing in the PORT0 PAD reg
|
|
+ */
|
|
+ if (priv->switch_id == QCA8K_ID_QCA8327 ||
|
|
+ priv->switch_id == QCA8K_ID_QCA8337)
|
|
+ reg = QCA8K_REG_PORT0_PAD_CTRL;
|
|
+
|
|
+ val = 0;
|
|
+
|
|
+ /* SGMII Clock phase configuration */
|
|
+ if (priv->sgmii_rx_clk_falling_edge)
|
|
+ val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
|
|
+
|
|
+ if (priv->sgmii_tx_clk_falling_edge)
|
|
+ val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
|
|
+
|
|
+ if (val)
|
|
+ ret = qca8k_rmw(priv, reg,
|
|
+ QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
|
|
+ QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
|
|
+ val);
|
|
break;
|
|
default:
|
|
dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
|
|
--- a/drivers/net/dsa/qca8k.h
|
|
+++ b/drivers/net/dsa/qca8k.h
|
|
@@ -35,6 +35,8 @@
|
|
#define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8)
|
|
#define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8)
|
|
#define QCA8K_REG_PORT0_PAD_CTRL 0x004
|
|
+#define QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE BIT(19)
|
|
+#define QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE BIT(18)
|
|
#define QCA8K_REG_PORT5_PAD_CTRL 0x008
|
|
#define QCA8K_REG_PORT6_PAD_CTRL 0x00c
|
|
#define QCA8K_PORT_PAD_RGMII_EN BIT(26)
|
|
@@ -260,6 +262,8 @@ struct qca8k_priv {
|
|
u8 switch_revision;
|
|
u8 rgmii_tx_delay;
|
|
u8 rgmii_rx_delay;
|
|
+ bool sgmii_rx_clk_falling_edge;
|
|
+ bool sgmii_tx_clk_falling_edge;
|
|
bool legacy_phy_port_mapping;
|
|
struct regmap *regmap;
|
|
struct mii_bus *bus;
|