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e58cd453d5
Add kernel support for SAMA7G5 by back-porting mainline kernel patches. Among SAMA7G5 features could be remembered: - ARM Cortex-A7 - double data rate multi-port dynamic RAM controller supporting DDR2, DDR3, DDR3L, LPDDR2, LPDDR3 up to 533MHz - peripherals for audio, video processing - 1 gigabit + 1 megabit Ethernet controllers - 6 CAN controllers - trust zone support - DVFS for CPU - criptography IPs Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
34 lines
991 B
Diff
34 lines
991 B
Diff
From 2b522a22243938dd7613e09c954172b1fa6217f5 Mon Sep 17 00:00:00 2001
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From: Claudiu Beznea <claudiu.beznea@microchip.com>
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Date: Thu, 15 Apr 2021 13:50:01 +0300
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Subject: [PATCH 211/247] ARM: at91: pm: wait for ddr power mode off
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Wait for DDR power mode off before shutting down the core.
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Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
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Link: https://lore.kernel.org/r/20210415105010.569620-16-claudiu.beznea@microchip.com
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---
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arch/arm/mach-at91/pm_suspend.S | 5 +++++
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1 file changed, 5 insertions(+)
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diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
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index 9c9e08fd8300..7396e18dd7e5 100644
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--- a/arch/arm/mach-at91/pm_suspend.S
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+++ b/arch/arm/mach-at91/pm_suspend.S
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@@ -980,6 +980,11 @@ ulp_exit:
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mov tmp1, #0x1
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str tmp1, [r0, #0x10]
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+ /* Wait for it. */
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+1: ldr tmp1, [r0, #0x10]
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+ tst tmp1, #0x1
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+ beq 1b
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+
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/* Shutdown */
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ldr r0, .shdwc
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mov tmp1, #0xA5000000
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--
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2.32.0
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