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synced 2025-11-04 06:54:27 -05:00
48 lines
1.2 KiB
Diff
48 lines
1.2 KiB
Diff
--- a/arch/mips/ath79/common.h
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+++ b/arch/mips/ath79/common.h
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@@ -26,6 +26,7 @@ void ath79_ddr_wb_flush(unsigned int reg
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void ath79_gpio_function_enable(u32 mask);
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void ath79_gpio_function_disable(u32 mask);
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void ath79_gpio_function_setup(u32 set, u32 clear);
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+void ath79_gpio_output_select(unsigned gpio, u8 val);
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void ath79_gpio_init(void);
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#endif /* __ATH79_COMMON_H */
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--- a/arch/mips/ath79/gpio.c
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+++ b/arch/mips/ath79/gpio.c
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@@ -184,6 +184,34 @@ void ath79_gpio_function_setup(u32 set,
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spin_unlock_irqrestore(&ath79_gpio_lock, flags);
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}
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+void __init ath79_gpio_output_select(unsigned gpio, u8 val)
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+{
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+ void __iomem *base = ath79_gpio_base;
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+ unsigned long flags;
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+ unsigned int reg;
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+ u32 t, s;
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+
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+ BUG_ON(!soc_is_ar934x());
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+
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+ if (gpio >= AR934X_GPIO_COUNT)
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+ return;
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+
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+ reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4);
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+ s = 8 * (gpio % 4);
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+
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+ spin_lock_irqsave(&ath79_gpio_lock, flags);
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+
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+ t = __raw_readl(base + reg);
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+ t &= ~(0xff << s);
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+ t |= val << s;
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+ __raw_writel(t, base + reg);
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+
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+ /* flush write */
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+ (void) __raw_readl(base + reg);
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+
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+ spin_unlock_irqrestore(&ath79_gpio_lock, flags);
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+}
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+
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void __init ath79_gpio_init(void)
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{
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int err;
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