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			507 lines
		
	
	
		
			16 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
			
		
		
	
	
			507 lines
		
	
	
		
			16 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
| --- a/net80211/ieee80211_rate.h
 | |
| +++ b/net80211/ieee80211_rate.h
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| @@ -81,6 +81,8 @@ struct ieee80211vap;
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|  
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|  /* Multi-rare retry: 3 additional rate/retry pairs */
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|  struct ieee80211_mrr {
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| +	int rate0;
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| +	int retries0;
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|  	int rate1;
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|  	int retries1;
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|  	int rate2;
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| @@ -142,7 +144,7 @@ struct ieee80211_rate_ops {
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|  	 * for packets that were successfully sent and for those that
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|  	 * failed (consult the descriptor for details). */
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|  	void (*tx_complete)(struct ath_softc *sc, struct ath_node *an,
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| -			    const struct ath_buf *bf);
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| +			    const struct ath_buf *bf, const struct ieee80211_mrr *mrr);
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|  };
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|  
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|  struct ath_ratectrl {
 | |
| --- a/ath/if_ath.c
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| +++ b/ath/if_ath.c
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| @@ -8638,6 +8638,8 @@ ath_tx_processq(struct ath_softc *sc, st
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|  
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|  		ni = bf->bf_node;
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|  		if (ni != NULL) {
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| +			struct ieee80211_mrr mrr;
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| +
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|  			an = ATH_NODE(ni);
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|  			if (ts->ts_status == 0) {
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|  				u_int8_t txant = ts->ts_antenna;
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| @@ -8690,15 +8692,43 @@ ath_tx_processq(struct ath_softc *sc, st
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|  			lr = ts->ts_longretry;
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|  			sc->sc_stats.ast_tx_shortretry += sr;
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|  			sc->sc_stats.ast_tx_longretry += lr;
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| +			memset(&mrr, 0, sizeof(mrr));
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| +
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| +			switch(ah->ah_macType) {
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| +			case 5210:
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| +			case 5211:
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| +				goto skip_mrr;
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| +
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| +			case 5212:
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| +				mrr.rate0 = sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate0)].ieeerate;
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| +				mrr.rate1 = sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate1)].ieeerate;
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| +				mrr.rate2 = sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate2)].ieeerate;
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| +				mrr.rate3 = sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate3)].ieeerate;
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| +				break;
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| +
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| +			case 5416:
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| +				mrr.rate0 = sc->sc_hwmap[MS(ds->ds_ctl3, AR5416_XmitRate0)].ieeerate;
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| +				mrr.rate1 = sc->sc_hwmap[MS(ds->ds_ctl3, AR5416_XmitRate1)].ieeerate;
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| +				mrr.rate2 = sc->sc_hwmap[MS(ds->ds_ctl3, AR5416_XmitRate2)].ieeerate;
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| +				mrr.rate3 = sc->sc_hwmap[MS(ds->ds_ctl3, AR5416_XmitRate3)].ieeerate;
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| +				break;
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| +			}
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| +
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| +			mrr.retries0 = MS(ds->ds_ctl2, AR_XmitDataTries0);
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| +			mrr.retries1 = MS(ds->ds_ctl2, AR_XmitDataTries1);
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| +			mrr.retries2 = MS(ds->ds_ctl2, AR_XmitDataTries2);
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| +			mrr.retries3 = MS(ds->ds_ctl2, AR_XmitDataTries3);
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| +
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|  			/*
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|  			 * Hand the descriptor to the rate control algorithm
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|  			 * if the frame wasn't dropped for filtering or sent
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|  			 * w/o waiting for an ack.  In those cases the rssi
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|  			 * and retry counts will be meaningless.
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|  			 */
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| +skip_mrr:
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|  			if ((ts->ts_status & HAL_TXERR_FILT) == 0 &&
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|  			    (bf->bf_flags & HAL_TXDESC_NOACK) == 0)
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| -				sc->sc_rc->ops->tx_complete(sc, an, bf);
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| +				sc->sc_rc->ops->tx_complete(sc, an, bf, &mrr);
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|  		}
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|  
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|  		bus_unmap_single(sc->sc_bdev, bf->bf_skbaddr,
 | |
| --- a/ath/if_athvar.h
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| +++ b/ath/if_athvar.h
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| @@ -595,6 +595,46 @@ struct ath_vap {
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|  	(_tqs)->axq_link = NULL; \
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|  } while (0)
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|  
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| +/*
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| + * Definitions for pulling the rate and trie counts from
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| + * a 5212 h/w descriptor. These Don't belong here; the
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| + * driver should record this information so the rate control
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| + * code doesn't go groveling around in the descriptor bits.
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| + */
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| +#define	ds_ctl2	ds_hw[0]
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| +#define	ds_ctl3	ds_hw[1]
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| +
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| +/* TX ds_ctl3 */
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| +#define	AR_XmitDataTries0	0x000f0000	/* series 0 max attempts */
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| +#define	AR_XmitDataTries0_S	16
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| +#define	AR_XmitDataTries1	0x00f00000	/* series 1 max attempts */
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| +#define	AR_XmitDataTries1_S	20
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| +#define	AR_XmitDataTries2	0x0f000000	/* series 2 max attempts */
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| +#define	AR_XmitDataTries2_S	24
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| +#define	AR_XmitDataTries3	0xf0000000	/* series 3 max attempts */
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| +#define	AR_XmitDataTries3_S	28
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| +
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| +/* TX ds_ctl3 */
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| +#define	AR_XmitRate0		0x0000001f	/* series 0 tx rate */
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| +#define	AR_XmitRate0_S		0
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| +#define	AR_XmitRate1		0x000003e0	/* series 1 tx rate */
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| +#define	AR_XmitRate1_S		5
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| +#define	AR_XmitRate2		0x00007c00	/* series 2 tx rate */
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| +#define	AR_XmitRate2_S		10
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| +#define	AR_XmitRate3		0x000f8000	/* series 3 tx rate */
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| +#define	AR_XmitRate3_S		15
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| +
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| +#define AR5416_XmitRate0        0x000000ff
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| +#define AR5416_XmitRate0_S      0
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| +#define AR5416_XmitRate1        0x0000ff00
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| +#define AR5416_XmitRate1_S      8
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| +#define AR5416_XmitRate2        0x00ff0000
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| +#define AR5416_XmitRate2_S      16
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| +#define AR5416_XmitRate3        0xff000000
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| +#define AR5416_XmitRate3_S      24
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| +
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| +#define MS(_v, _f)	(((_v) & (_f)) >> _f##_S)
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| +
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|  /* 
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|   * concat buffers from one queue to other
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|   */
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| --- a/ath_rate/amrr/amrr.c
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| +++ b/ath_rate/amrr/amrr.c
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| @@ -123,7 +123,8 @@ ath_rate_get_mrr(struct ath_softc *sc, s
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|  
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|  static void
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|  ath_rate_tx_complete(struct ath_softc *sc,
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| -	struct ath_node *an, const struct ath_buf *bf)
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| +	struct ath_node *an, const struct ath_buf *bf,
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| +	const struct ieee80211_mrr *mrr)
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|  {
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|  	struct amrr_node *amn = ATH_NODE_AMRR(an);
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|  	const struct ath_tx_status *ts = &bf->bf_dsstatus.ds_txstat;
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| --- a/ath_rate/minstrel/minstrel.c
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| +++ b/ath_rate/minstrel/minstrel.c
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| @@ -333,7 +333,8 @@ ath_rate_get_mrr(struct ath_softc *sc, s
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|  
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|  static void
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|  ath_rate_tx_complete(struct ath_softc *sc,
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| -		struct ath_node *an, const struct ath_buf *bf)
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| +		struct ath_node *an, const struct ath_buf *bf,
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| +		const struct ieee80211_mrr *mrr)
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|  {
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|  		struct minstrel_node *sn = ATH_NODE_MINSTREL(an);
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|  		struct ieee80211com *ic = &sc->sc_ic;
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| @@ -341,12 +342,9 @@ ath_rate_tx_complete(struct ath_softc *s
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|  		const struct ath_desc *ds = &bf->bf_desc[0];
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|  		int final_rate = 0;
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|  		int tries = 0;
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| -		int mrr;
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| +		int use_mrr;
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|  		int final_ndx;
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| -		int rate0, tries0, ndx0;
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| -		int rate1, tries1, ndx1;
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| -		int rate2, tries2, ndx2;
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| -		int rate3, tries3, ndx3;
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| +		int ndx0, ndx1, ndx2, ndx3;
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|  
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|  		/* This is the index in the retry chain we finish at.
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|  		 * With no retransmits, it is always 0.
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| @@ -376,9 +374,9 @@ ath_rate_tx_complete(struct ath_softc *s
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|  		if (!ts->ts_status)  /* Success when sending a packet*/
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|  			sn->rs_ratesuccess[final_ndx]++;
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|  
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| -		mrr = sc->sc_mrretry && !(ic->ic_flags & IEEE80211_F_USEPROT) && ENABLE_MRR;
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| +		use_mrr = sc->sc_mrretry && !(ic->ic_flags & IEEE80211_F_USEPROT) && ENABLE_MRR;
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|  
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| -		if (!mrr) {
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| +		if (!use_mrr) {
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|  			if ((0 <= final_ndx) && (final_ndx < sn->num_rates)) {
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|  				sn->rs_rateattempts[final_ndx] += tries; /* only one rate was used */
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|  			}
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| @@ -388,47 +386,36 @@ ath_rate_tx_complete(struct ath_softc *s
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|  		/* Now, query the hal/hardware to find out the contents of the multirate retry chain.
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|  		 * If we have it set to 6,3,2,2, this call will always return 6,3,2,2. For some packets, we can
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|  		 * get a mrr of 0, -1, -1, -1, which indicates there is no chain installed for that packet */
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| -		rate0 = sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate0)].ieeerate;
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| -		tries0 = MS(ds->ds_ctl2, AR_XmitDataTries0);
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| -		ndx0 = rate_to_ndx(sn, rate0);
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| +		ndx0 = rate_to_ndx(sn, mrr->rate0);
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| +		ndx1 = rate_to_ndx(sn, mrr->rate1);
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| +		ndx2 = rate_to_ndx(sn, mrr->rate2);
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| +		ndx3 = rate_to_ndx(sn, mrr->rate3);
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|  
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| -		rate1 = sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate1)].ieeerate;
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| -		tries1 = MS(ds->ds_ctl2, AR_XmitDataTries1);
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| -		ndx1 = rate_to_ndx(sn, rate1);
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| -
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| -		rate2 = sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate2)].ieeerate;
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| -		tries2 = MS(ds->ds_ctl2, AR_XmitDataTries2);
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| -		ndx2 = rate_to_ndx(sn, rate2);
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| -
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| -		rate3 = sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate3)].ieeerate;
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| -		tries3 = MS(ds->ds_ctl2, AR_XmitDataTries3);
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| -		ndx3 = rate_to_ndx(sn, rate3);
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| -
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| -		sn->rs_rateattempts[ndx0] += MIN(tries, tries0);
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| -		if (tries <= tries0)
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| +		sn->rs_rateattempts[ndx0] += MIN(tries, mrr->retries0);
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| +		if (tries <= mrr->retries0)
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|  			return;
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|  
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| -		if (tries1 < 0)
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| +		if (mrr->retries1 < 0)
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|  			return;
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| -		tries = tries - tries0;
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| -		sn->rs_rateattempts[ndx1] += MIN(tries, tries1);
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| -		if (tries <= tries1)
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| +		tries = tries - mrr->retries0;
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| +		sn->rs_rateattempts[ndx1] += MIN(tries, mrr->retries1);
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| +		if (tries <= mrr->retries1)
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|  			return;
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|  
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|  		if (bf->rcflags)
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|  			sn->sample_count++;
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|  
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| -		if  (tries2 < 0)
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| +		if (mrr->retries2 < 0)
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|  			return;
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| -		tries = tries - tries1;
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| -		sn->rs_rateattempts[ndx2] += MIN(tries, tries2);
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| -		if (tries <= tries2)
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| +		tries = tries - mrr->retries1;
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| +		sn->rs_rateattempts[ndx2] += MIN(tries, mrr->retries2);
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| +		if (tries <= mrr->retries2)
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|  			return;
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|  
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| -		if  (tries3 < 0)
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| +		if (mrr->retries3 < 0)
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|  			return;
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| -		tries = tries - tries2;
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| -		sn->rs_rateattempts[ndx3] += MIN(tries, tries3);
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| +		tries = tries - mrr->retries2;
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| +		sn->rs_rateattempts[ndx3] += MIN(tries, mrr->retries3);
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|  }
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|  
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|  static void
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| --- a/ath_rate/minstrel/minstrel.h
 | |
| +++ b/ath_rate/minstrel/minstrel.h
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| @@ -172,36 +172,6 @@ struct minstrel_node {
 | |
|  
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|  #define	ATH_NODE_MINSTREL(an)	((struct minstrel_node *)&an[1])
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|  
 | |
| -/*
 | |
| - * Definitions for pulling the rate and trie counts from
 | |
| - * a 5212 h/w descriptor. These Don't belong here; the
 | |
| - * driver should record this information so the rate control
 | |
| - * code doesn't go groveling around in the descriptor bits.
 | |
| - */
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| -#define	ds_ctl2	ds_hw[0]
 | |
| -#define	ds_ctl3	ds_hw[1]
 | |
| -
 | |
| -/* TX ds_ctl3 */
 | |
| -#define	AR_XmitDataTries0	0x000f0000	/* series 0 max attempts */
 | |
| -#define	AR_XmitDataTries0_S	16
 | |
| -#define	AR_XmitDataTries1	0x00f00000	/* series 1 max attempts */
 | |
| -#define	AR_XmitDataTries1_S	20
 | |
| -#define	AR_XmitDataTries2	0x0f000000	/* series 2 max attempts */
 | |
| -#define	AR_XmitDataTries2_S	24
 | |
| -#define	AR_XmitDataTries3	0xf0000000	/* series 3 max attempts */
 | |
| -#define	AR_XmitDataTries3_S	28
 | |
| -
 | |
| -/* TX ds_ctl3 */
 | |
| -#define	AR_XmitRate0		0x0000001f	/* series 0 tx rate */
 | |
| -#define	AR_XmitRate0_S		0
 | |
| -#define	AR_XmitRate1		0x000003e0	/* series 1 tx rate */
 | |
| -#define	AR_XmitRate1_S		5
 | |
| -#define	AR_XmitRate2		0x00007c00	/* series 2 tx rate */
 | |
| -#define	AR_XmitRate2_S		10
 | |
| -#define	AR_XmitRate3		0x000f8000	/* series 3 tx rate */
 | |
| -#define	AR_XmitRate3_S		15
 | |
| -
 | |
| -#define MS(_v, _f)	(((_v) & (_f)) >> _f##_S)
 | |
|  #endif /* _DEV_ATH_RATE_MINSTEL_H */
 | |
|  
 | |
|  /* The comment below is magic for those who use emacs to edit this file. */
 | |
| --- a/ath_rate/onoe/onoe.c
 | |
| +++ b/ath_rate/onoe/onoe.c
 | |
| @@ -137,7 +137,8 @@ ath_rate_get_mrr(struct ath_softc *sc, s
 | |
|  
 | |
|  static void
 | |
|  ath_rate_tx_complete(struct ath_softc *sc,
 | |
| -	struct ath_node *an, const struct ath_buf *bf)
 | |
| +	struct ath_node *an, const struct ath_buf *bf,
 | |
| +	const struct ieee80211_mrr *mrr)
 | |
|  {
 | |
|  	struct onoe_node *on = ATH_NODE_ONOE(an);
 | |
|  	const struct ath_tx_status *ts = &bf->bf_dsstatus.ds_txstat;
 | |
| --- a/ath_rate/sample/sample.c
 | |
| +++ b/ath_rate/sample/sample.c
 | |
| @@ -178,10 +178,6 @@ static __inline int best_rate_ndx(struct
 | |
|  		    !sn->stats[size_bin][x].packets_acked))
 | |
|  			continue;
 | |
|  
 | |
| -		/* 9 megabits never works better than 12 */
 | |
| -		if (sn->rates[x].rate == 18)
 | |
| -			continue;
 | |
| -
 | |
|  		/* don't use a bit-rate that has been failing */
 | |
|  		if (sn->stats[size_bin][x].successive_failures > 3)
 | |
|  			continue;
 | |
| @@ -234,10 +230,6 @@ pick_sample_ndx(struct sample_node *sn,
 | |
|  		if (sn->rates[ndx].rate > 22 && ndx > current_ndx + 2)
 | |
|  			continue;
 | |
|  
 | |
| -		/* 9 megabits never works better than 12 */
 | |
| -		if (sn->rates[ndx].rate == 18)
 | |
| -			continue;
 | |
| -
 | |
|  		/* if we're using 11 megabits, only sample up to 12 megabits
 | |
|  		 */
 | |
|  		if (sn->rates[current_ndx].rate == 22 && ndx > current_ndx + 1)
 | |
| @@ -531,7 +523,8 @@ update_stats(struct ath_softc *sc, struc
 | |
|  
 | |
|  static void
 | |
|  ath_rate_tx_complete(struct ath_softc *sc,
 | |
| -	struct ath_node *an, const struct ath_buf *bf)
 | |
| +	struct ath_node *an, const struct ath_buf *bf,
 | |
| +	const struct ieee80211_mrr *mrr)
 | |
|  {
 | |
|  	struct sample_node *sn = ATH_NODE_SAMPLE(an);
 | |
|  	struct ieee80211com *ic = &sc->sc_ic;
 | |
| @@ -541,7 +534,7 @@ ath_rate_tx_complete(struct ath_softc *s
 | |
|  	unsigned int short_tries;
 | |
|  	unsigned int long_tries;
 | |
|  	unsigned int frame_size;
 | |
| -	unsigned int mrr;
 | |
| +	unsigned int use_mrr;
 | |
|  
 | |
|  	final_rate = sc->sc_hwmap[ts->ts_rate &~ HAL_TXSTAT_ALTRATE].ieeerate;
 | |
|  	short_tries = ts->ts_shortretry + 1;
 | |
| @@ -557,7 +550,7 @@ ath_rate_tx_complete(struct ath_softc *s
 | |
|  		return;
 | |
|  	}
 | |
|  
 | |
| -	mrr = sc->sc_mrretry && !(ic->ic_flags & IEEE80211_F_USEPROT) && ENABLE_MRR;
 | |
| +	use_mrr = sc->sc_mrretry && !(ic->ic_flags & IEEE80211_F_USEPROT) && ENABLE_MRR;
 | |
|  
 | |
|  
 | |
|  	if (sc->sc_mrretry && ts->ts_status) {
 | |
| @@ -566,22 +559,15 @@ ath_rate_tx_complete(struct ath_softc *s
 | |
|  			dev_info,
 | |
|  			MAC_ADDR(an->an_node.ni_macaddr),
 | |
|  			bin_to_size(size_to_bin(frame_size)),
 | |
| -			sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate0)].ieeerate,
 | |
| -				MS(ds->ds_ctl2, AR_XmitDataTries0),
 | |
| -			sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate1)].ieeerate,
 | |
| -				MS(ds->ds_ctl2, AR_XmitDataTries1),
 | |
| -			sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate2)].ieeerate,
 | |
| -				MS(ds->ds_ctl2, AR_XmitDataTries2),
 | |
| -			sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate3)].ieeerate,
 | |
| -				MS(ds->ds_ctl2, AR_XmitDataTries3),
 | |
| +			mrr->rate0,
 | |
| +			mrr->rate1,
 | |
| +			mrr->rate2,
 | |
| +			mrr->rate3,
 | |
|  			ts->ts_status ? "FAIL" : "OK",
 | |
|  			short_tries, long_tries);
 | |
|  	}
 | |
|  
 | |
| -	mrr = sc->sc_mrretry && !(ic->ic_flags & IEEE80211_F_USEPROT) && ENABLE_MRR;
 | |
| -
 | |
| -
 | |
| -	if (!mrr || !(ts->ts_rate & HAL_TXSTAT_ALTRATE)) {
 | |
| +	if (!use_mrr || !(ts->ts_rate & HAL_TXSTAT_ALTRATE)) {
 | |
|  		/* only one rate was used */
 | |
|  		int ndx = rate_to_ndx(sn, final_rate);
 | |
|  		if ((ndx >= 0) && (ndx < sn->num_rates)) {
 | |
| @@ -593,7 +579,6 @@ ath_rate_tx_complete(struct ath_softc *s
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|  				short_tries, long_tries, ts->ts_status);
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|  		}
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|  	} else {
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| -		unsigned int rate[4], tries[4];
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|  		int ndx[4];
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|  		int finalTSIdx = ts->ts_finaltsi;
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|  
 | |
| @@ -601,21 +586,10 @@ ath_rate_tx_complete(struct ath_softc *s
 | |
|  		 * Process intermediate rates that failed.
 | |
|  		 */
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|  
 | |
| -		rate[0] = sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate0)].ieeerate;
 | |
| -		tries[0] = MS(ds->ds_ctl2, AR_XmitDataTries0);
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| -		ndx[0] = rate_to_ndx(sn, rate[0]);
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| -
 | |
| -		rate[1] = sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate1)].ieeerate;
 | |
| -		tries[1] = MS(ds->ds_ctl2, AR_XmitDataTries1);
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| -		ndx[1] = rate_to_ndx(sn, rate[1]);
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| -
 | |
| -		rate[2] = sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate2)].ieeerate;
 | |
| -		tries[2] = MS(ds->ds_ctl2, AR_XmitDataTries2);
 | |
| -		ndx[2] = rate_to_ndx(sn, rate[2]);
 | |
| -
 | |
| -		rate[3] = sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate3)].ieeerate;
 | |
| -		tries[3] = MS(ds->ds_ctl2, AR_XmitDataTries3);
 | |
| -		ndx[3] = rate_to_ndx(sn, rate[3]);
 | |
| +		ndx[0] = rate_to_ndx(sn, mrr->rate0);
 | |
| +		ndx[1] = rate_to_ndx(sn, mrr->rate1);
 | |
| +		ndx[2] = rate_to_ndx(sn, mrr->rate2);
 | |
| +		ndx[3] = rate_to_ndx(sn, mrr->rate3);
 | |
|  
 | |
|  #if 0
 | |
|  		DPRINTF(sc, ATH_DEBUG_RATE, "%s: " MAC_FMT " size %u finaltsidx %u tries %u status %u rate/try %u/%u %u/%u %u/%u %u/%u\n",
 | |
| @@ -636,43 +610,43 @@ ath_rate_tx_complete(struct ath_softc *s
 | |
|  		 * sample higher rates 1 try at a time doing so
 | |
|  		 * may unfairly penalize them.
 | |
|  		 */
 | |
| -		if (tries[0] && ndx[0] >= 0) {
 | |
| +		if (mrr->retries0 && ndx[0] >= 0) {
 | |
|  			update_stats(sc, an, frame_size,
 | |
| -				ndx[0], tries[0],
 | |
| -				ndx[1], tries[1],
 | |
| -				ndx[2], tries[2],
 | |
| -				ndx[3], tries[3],
 | |
| +				ndx[0], mrr->retries0,
 | |
| +				ndx[1], mrr->retries1,
 | |
| +				ndx[2], mrr->retries2,
 | |
| +				ndx[3], mrr->retries3,
 | |
|  				short_tries, long_tries,
 | |
| -				long_tries > tries[0]);
 | |
| -			long_tries -= tries[0];
 | |
| +				long_tries > mrr->retries0);
 | |
| +			long_tries -= mrr->retries0;
 | |
|  
 | |
|  		}
 | |
|  
 | |
| -		if (tries[1] && ndx[1] >= 0 && finalTSIdx > 0) {
 | |
| +		if (mrr->retries1 && ndx[1] >= 0 && finalTSIdx > 0) {
 | |
|  			update_stats(sc, an, frame_size,
 | |
| -				ndx[1], tries[1],
 | |
| -				ndx[2], tries[2],
 | |
| -				ndx[3], tries[3],
 | |
| +				ndx[1], mrr->retries1,
 | |
| +				ndx[2], mrr->retries2,
 | |
| +				ndx[3], mrr->retries3,
 | |
|  				0, 0,
 | |
|  				short_tries, long_tries,
 | |
|  				ts->ts_status);
 | |
| -			long_tries -= tries[1];
 | |
| +			long_tries -= mrr->retries1;
 | |
|  		}
 | |
|  
 | |
| -		if (tries[2] && ndx[2] >= 0 && finalTSIdx > 1) {
 | |
| +		if (mrr->retries2 && ndx[2] >= 0 && finalTSIdx > 1) {
 | |
|  			update_stats(sc, an, frame_size,
 | |
| -				ndx[2], tries[2],
 | |
| -				ndx[3], tries[3],
 | |
| +				ndx[2], mrr->retries2,
 | |
| +				ndx[3], mrr->retries3,
 | |
|  				0, 0,
 | |
|  				0, 0,
 | |
|  				short_tries, long_tries,
 | |
|  				ts->ts_status);
 | |
| -			long_tries -= tries[2];
 | |
| +			long_tries -= mrr->retries2;
 | |
|  		}
 | |
|  
 | |
| -		if (tries[3] && ndx[3] >= 0 && finalTSIdx > 2) {
 | |
| +		if (mrr->retries3 && ndx[3] >= 0 && finalTSIdx > 2) {
 | |
|  			update_stats(sc, an, frame_size,
 | |
| -				ndx[3], tries[3],
 | |
| +				ndx[3], mrr->retries3,
 | |
|  				0, 0,
 | |
|  				0, 0,
 | |
|  				0, 0,
 | |
| --- a/ath_rate/sample/sample.h
 | |
| +++ b/ath_rate/sample/sample.h
 | |
| @@ -98,35 +98,4 @@ struct sample_node {
 | |
|  };
 | |
|  #define	ATH_NODE_SAMPLE(an)	((struct sample_node *)&an[1])
 | |
|  
 | |
| -/*
 | |
| - * Definitions for pulling the rate and trie counts from
 | |
| - * a 5212 h/w descriptor. These Don't belong here; the
 | |
| - * driver should record this information so the rate control
 | |
| - * code doesn't go groveling around in the descriptor bits.
 | |
| - */
 | |
| -#define	ds_ctl2	ds_hw[0]
 | |
| -#define	ds_ctl3	ds_hw[1]
 | |
| -
 | |
| -/* TX ds_ctl3 */
 | |
| -#define	AR_XmitDataTries0	0x000f0000	/* series 0 max attempts */
 | |
| -#define	AR_XmitDataTries0_S	16
 | |
| -#define	AR_XmitDataTries1	0x00f00000	/* series 1 max attempts */
 | |
| -#define	AR_XmitDataTries1_S	20
 | |
| -#define	AR_XmitDataTries2	0x0f000000	/* series 2 max attempts */
 | |
| -#define	AR_XmitDataTries2_S	24
 | |
| -#define	AR_XmitDataTries3	0xf0000000	/* series 3 max attempts */
 | |
| -#define	AR_XmitDataTries3_S	28
 | |
| -
 | |
| -/* TX ds_ctl3 */
 | |
| -#define	AR_XmitRate0		0x0000001f	/* series 0 tx rate */
 | |
| -#define	AR_XmitRate0_S		0
 | |
| -#define	AR_XmitRate1		0x000003e0	/* series 1 tx rate */
 | |
| -#define	AR_XmitRate1_S		5
 | |
| -#define	AR_XmitRate2		0x00007c00	/* series 2 tx rate */
 | |
| -#define	AR_XmitRate2_S		10
 | |
| -#define	AR_XmitRate3		0x000f8000	/* series 3 tx rate */
 | |
| -#define	AR_XmitRate3_S		15
 | |
| -
 | |
| -#define MS(_v, _f)	(((_v) & (_f)) >> _f##_S)
 | |
| -
 | |
|  #endif /* _DEV_ATH_RATE_SAMPLE_H */
 |