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git://git.openwrt.org/openwrt/openwrt.git
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301 lines
5.9 KiB
Diff
301 lines
5.9 KiB
Diff
From dd4f939bb7c30f9256a35d31de673241ead350ab Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Fri, 24 Jan 2014 17:01:22 +0100
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Subject: [PATCH 208/215] MIPS: ralink: add MT7621 dts file
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/ralink/dts/Makefile | 1 +
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arch/mips/ralink/dts/mt7621.dtsi | 257 ++++++++++++++++++++++++++++++++++
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arch/mips/ralink/dts/mt7621_eval.dts | 16 +++
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3 files changed, 274 insertions(+)
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create mode 100644 arch/mips/ralink/dts/mt7621.dtsi
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create mode 100644 arch/mips/ralink/dts/mt7621_eval.dts
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--- a/arch/mips/ralink/dts/Makefile
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+++ b/arch/mips/ralink/dts/Makefile
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@@ -2,3 +2,4 @@ obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_
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obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
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obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o
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obj-$(CONFIG_DTB_MT7620A_EVAL) := mt7620a_eval.dtb.o
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+obj-$(CONFIG_DTB_MT7621_EVAL) := mt7621_eval.dtb.o
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--- /dev/null
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+++ b/arch/mips/ralink/dts/mt7621.dtsi
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@@ -0,0 +1,257 @@
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+/ {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "ralink,mtk7620a-soc";
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+
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+ cpus {
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+ cpu@0 {
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+ compatible = "mips,mips24KEc";
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+ };
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+ };
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+
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+ cpuintc: cpuintc@0 {
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+ #address-cells = <0>;
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+ #interrupt-cells = <1>;
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+ interrupt-controller;
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+ compatible = "mti,cpu-interrupt-controller";
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+ };
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+
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+ palmbus@1E000000 {
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+ compatible = "palmbus";
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+ reg = <0x1E000000 0x100000>;
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+ ranges = <0x0 0x1E000000 0x0FFFFF>;
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+
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ sysc@0 {
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+ compatible = "mtk,mt7621-sysc";
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+ reg = <0x0 0x100>;
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+ };
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+
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+ wdt@100 {
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+ compatible = "mtk,mt7621-wdt";
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+ reg = <0x100 0x100>;
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+ };
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+
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+ gpio@600 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ compatible = "mtk,mt7621-gpio";
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+ reg = <0x600 0x100>;
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+
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+ gpio0: bank@0 {
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+ reg = <0>;
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+ compatible = "mtk,mt7621-gpio-bank";
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ };
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+
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+ gpio1: bank@1 {
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+ reg = <1>;
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+ compatible = "mtk,mt7621-gpio-bank";
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ };
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+
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+ gpio2: bank@2 {
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+ reg = <2>;
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+ compatible = "mtk,mt7621-gpio-bank";
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ };
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+ };
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+
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+ memc@5000 {
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+ compatible = "mtk,mt7621-memc";
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+ reg = <0x300 0x100>;
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+ };
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+
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+ uartlite@c00 {
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+ compatible = "ns16550a";
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+ reg = <0xc00 0x100>;
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+
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+ interrupt-parent = <&gic>;
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+ interrupts = <26>;
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+
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+ reg-shift = <2>;
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+ reg-io-width = <4>;
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+ no-loopback-test;
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+ };
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+
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+ uart@d00 {
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+ compatible = "ns16550a";
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+ reg = <0xd00 0x100>;
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+
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+ interrupt-parent = <&gic>;
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+ interrupts = <27>;
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+
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+ fifo-size = <16>;
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+ reg-shift = <2>;
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+ reg-io-width = <4>;
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+ no-loopback-test;
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+ };
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+
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+ spi@b00 {
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+ status = "okay";
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+
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+ compatible = "ralink,mt7621-spi";
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+ reg = <0xb00 0x100>;
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+
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+ resets = <&rstctrl 18>;
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+ reset-names = "spi";
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+
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+/* pinctrl-names = "default";
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+ pinctrl-0 = <&spi_pins>;*/
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+
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+ m25p80@0 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "en25q64";
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+ reg = <0 0>;
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+ linux,modalias = "m25p80", "en25q64";
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+ spi-max-frequency = <10000000>;
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+
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+ m25p,chunked-io;
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+
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+ partition@0 {
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+ label = "u-boot";
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+ reg = <0x0 0x30000>;
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+ read-only;
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+ };
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+
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+ partition@30000 {
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+ label = "u-boot-env";
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+ reg = <0x30000 0x10000>;
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+ read-only;
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+ };
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+
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+ factory: partition@40000 {
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+ label = "factory";
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+ reg = <0x40000 0x10000>;
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+ read-only;
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+ };
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+
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+ partition@50000 {
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+ label = "firmware";
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+ reg = <0x50000 0x7a0000>;
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+ };
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+
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+ partition@7f0000 {
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+ label = "test";
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+ reg = <0x7f0000 0x10000>;
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+ };
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+ };
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+ };
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+ };
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+
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+ rstctrl: rstctrl {
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+ compatible = "ralink,rt2880-reset";
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+ #reset-cells = <1>;
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+ };
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+
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+ sdhci@1E130000 {
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+ compatible = "ralink,mt7620a-sdhci";
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+ reg = <0x1E130000 4000>;
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+
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+ interrupt-parent = <&gic>;
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+ interrupts = <20>;
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+ };
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+
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+ xhci@1E1C0000 {
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+ compatible = "xhci-platform";
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+ reg = <0x1E1C0000 4000>;
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+
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+ interrupt-parent = <&gic>;
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+ interrupts = <22>;
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+ };
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+
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+ gic: gic@1fbc0000 {
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+ #address-cells = <0>;
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+ #interrupt-cells = <1>;
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+ interrupt-controller;
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+ compatible = "ralink,mt7621-gic";
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+ reg = < 0x1fbc0000 0x80 /* gic */
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+ 0x1fbf0000 0x8000 /* cpc */
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+ 0x1fbf8000 0x8000 /* gpmc */
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+ >;
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+ };
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+
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+ nand@1e003000 {
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+ compatible = "mtk,mt7621-nand";
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+ bank-width = <2>;
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+ reg = <0x1e003000 0x800
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+ 0x1e003800 0x800>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ partition@0 {
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+ label = "uboot";
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+ reg = <0x00000 0x80000>; /* 64 KB */
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+ };
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+ partition@80000 {
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+ label = "uboot_env";
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+ reg = <0x80000 0x80000>; /* 64 KB */
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+ };
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+ partition@100000 {
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+ label = "factory";
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+ reg = <0x100000 0x40000>;
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+ };
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+ partition@140000 {
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+ label = "rootfs";
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+ reg = <0x140000 0xec0000>;
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+ };
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+ };
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+
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+ ethernet@1e100000 {
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+ compatible = "ralink,mt7621-eth";
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+ reg = <0x1e100000 10000>;
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+
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ ralink,port-map = "llllw";
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+
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+ interrupt-parent = <&gic>;
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+ interrupts = <3>;
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+
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+/* resets = <&rstctrl 21 &rstctrl 23>;
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+ reset-names = "fe", "esw";
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+
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+ port@4 {
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+ compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
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+ reg = <4>;
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+
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+ status = "disabled";
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+ };
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+
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+ port@5 {
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+ compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
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+ reg = <5>;
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+
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+ status = "disabled";
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+ };
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+*/
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+ mdio-bus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ phy1f: ethernet-phy@1f {
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+ reg = <0x1f>;
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+ phy-mode = "rgmii";
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+
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+/* interrupt-parent = <&gic>;
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+ interrupts = <23>;
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+*/ };
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+ };
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+ };
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+
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+ gsw@1e110000 {
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+ compatible = "ralink,mt7620a-gsw";
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+ reg = <0x1e110000 8000>;
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+ };
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+};
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--- /dev/null
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+++ b/arch/mips/ralink/dts/mt7621_eval.dts
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@@ -0,0 +1,16 @@
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+/dts-v1/;
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+
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+/include/ "mt7621.dtsi"
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+
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+/ {
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+ compatible = "ralink,mt7621-eval-board", "ralink,mt7621-soc";
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+ model = "Ralink MT7621 evaluation board";
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+
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+ memory@0 {
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+ reg = <0x0 0x2000000>;
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+ };
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+
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+ chosen {
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+ bootargs = "console=ttyS0,57600";
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+ };
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+};
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