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324f234966
After booting, a "transmit queue 0 timed out" warning followed by a register dump was observed. The dump indicates that mtk_hw_init() does not initialize the EEECR during probe. This occurs because the netdev is allocated in mtk_add_mac(), which is called after mtk_hw_init(). Consequently, the EEECR register remains uninitialized until a reset is triggered, causing mtk_hw_init() to run again with a valid netdev, at which point the register is finally set. To address this, instead of modifying the probe sequence, latch the Tx LPI enable state and timer value, and move the EEECR register initialization to mtk_mac_link_up() to ensure proper setup when the interface comes up. Additionally, the splat reveals that LPI functionality is controlled by the MAC_MCR_EEE bits in the MCR register. Update mtk_set_eee() to modify these bits accordingly. Fixes:d8315d5358("kernel: backport Mediatek SoC EEE support") Fixes:edddbaf79c("kernel: Mediatek: set default EEE Tx LPI timer") Signed-off-by: Qingfang Deng <dqfext@gmail.com>
158 lines
4.9 KiB
Diff
158 lines
4.9 KiB
Diff
From 952d7325362ffbefa6ce5619fb4e53c2159ec7a7 Mon Sep 17 00:00:00 2001
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From: Qingfang Deng <dqfext@gmail.com>
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Date: Mon, 17 Feb 2025 17:40:21 +0800
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Subject: [PATCH] net: ethernet: mediatek: add EEE support
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Add EEE support to MediaTek SoC Ethernet. The register fields are
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similar to the ones in MT7531, except that the LPI threshold is in
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milliseconds.
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Signed-off-by: Qingfang Deng <dqfext@gmail.com>
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---
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drivers/net/ethernet/mediatek/mtk_eth_soc.c | 64 +++++++++++++++++++++
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drivers/net/ethernet/mediatek/mtk_eth_soc.h | 11 ++++
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2 files changed, 75 insertions(+)
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -786,6 +786,7 @@ static void mtk_mac_link_up(struct phyli
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mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
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mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 |
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+ MAC_MCR_EEE100M | MAC_MCR_EEE1G |
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MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC |
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MAC_MCR_FORCE_RX_FC);
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@@ -811,6 +812,15 @@ static void mtk_mac_link_up(struct phyli
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if (rx_pause)
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mcr |= MAC_MCR_FORCE_RX_FC;
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+ if (mode == MLO_AN_PHY && phy && mac->tx_lpi_enabled && phy_init_eee(phy, false) >= 0) {
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+ mcr |= MAC_MCR_EEE100M | MAC_MCR_EEE1G;
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+ mtk_w32(mac->hw,
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+ FIELD_PREP(MAC_EEE_WAKEUP_TIME_1000, 17) |
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+ FIELD_PREP(MAC_EEE_WAKEUP_TIME_100, 36) |
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+ FIELD_PREP(MAC_EEE_LPI_TXIDLE_THD, mac->txidle_thd_ms),
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+ MTK_MAC_EEECR(mac->id));
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+ }
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+
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mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK;
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mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
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}
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@@ -4476,6 +4486,61 @@ static int mtk_set_pauseparam(struct net
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return phylink_ethtool_set_pauseparam(mac->phylink, pause);
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}
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+static int mtk_get_eee(struct net_device *dev, struct ethtool_eee *eee)
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+{
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+ struct mtk_mac *mac = netdev_priv(dev);
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+ u32 reg;
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+ int ret;
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+
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+ ret = phylink_ethtool_get_eee(mac->phylink, eee);
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+ if (ret)
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+ return ret;
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+
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+ reg = mtk_r32(mac->hw, MTK_MAC_EEECR(mac->id));
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+ eee->tx_lpi_enabled = mac->tx_lpi_enabled;
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+ eee->tx_lpi_timer = FIELD_GET(MAC_EEE_LPI_TXIDLE_THD, reg) * 1000;
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+
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+ return 0;
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+}
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+
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+static int mtk_set_eee(struct net_device *dev, struct ethtool_eee *eee)
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+{
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+ struct mtk_mac *mac = netdev_priv(dev);
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+ u32 txidle_thd_ms, reg;
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+ int ret;
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+
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+ /* Tx idle timer in ms */
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+ txidle_thd_ms = DIV_ROUND_UP(eee->tx_lpi_timer, 1000);
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+ if (!FIELD_FIT(MAC_EEE_LPI_TXIDLE_THD, txidle_thd_ms))
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+ return -EINVAL;
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+
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+ reg = FIELD_PREP(MAC_EEE_LPI_TXIDLE_THD, txidle_thd_ms);
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+
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+ /* PHY Wake-up time, this field does not have a reset value, so use the
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+ * reset value from MT7531 (36us for 100BaseT and 17us for 1000BaseT).
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+ */
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+ reg |= FIELD_PREP(MAC_EEE_WAKEUP_TIME_1000, 17) |
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+ FIELD_PREP(MAC_EEE_WAKEUP_TIME_100, 36);
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+
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+ if (!txidle_thd_ms)
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+ /* Force LPI Mode without a delay */
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+ reg |= MAC_EEE_LPI_MODE;
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+
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+ ret = phylink_ethtool_set_eee(mac->phylink, eee);
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+ if (ret)
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+ return ret;
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+
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+ mac->tx_lpi_enabled = eee->tx_lpi_enabled;
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+ mac->txidle_thd_ms = txidle_thd_ms;
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+ mtk_w32(mac->hw, reg, MTK_MAC_EEECR(mac->id));
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+ if (eee->eee_enabled && eee->eee_active && eee->tx_lpi_enabled)
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+ mtk_m32(mac->hw, 0, MAC_MCR_EEE100M | MAC_MCR_EEE1G, MTK_MAC_MCR(mac->id));
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+ else
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+ mtk_m32(mac->hw, MAC_MCR_EEE100M | MAC_MCR_EEE1G, 0, MTK_MAC_MCR(mac->id));
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+
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+ return 0;
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+}
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+
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static u16 mtk_select_queue(struct net_device *dev, struct sk_buff *skb,
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struct net_device *sb_dev)
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{
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@@ -4508,6 +4573,8 @@ static const struct ethtool_ops mtk_etht
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.set_pauseparam = mtk_set_pauseparam,
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.get_rxnfc = mtk_get_rxnfc,
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.set_rxnfc = mtk_set_rxnfc,
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+ .get_eee = mtk_get_eee,
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+ .set_eee = mtk_set_eee,
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};
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static const struct net_device_ops mtk_netdev_ops = {
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@@ -4568,6 +4635,8 @@ static int mtk_add_mac(struct mtk_eth *e
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}
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mac = netdev_priv(eth->netdev[id]);
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eth->mac[id] = mac;
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+ mac->tx_lpi_enabled = true;
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+ mac->txidle_thd_ms = 1;
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mac->id = id;
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mac->hw = eth;
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mac->of_node = np;
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -453,6 +453,8 @@
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#define MAC_MCR_RX_FIFO_CLR_DIS BIT(12)
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#define MAC_MCR_BACKOFF_EN BIT(9)
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#define MAC_MCR_BACKPR_EN BIT(8)
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+#define MAC_MCR_EEE1G BIT(7)
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+#define MAC_MCR_EEE100M BIT(6)
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#define MAC_MCR_FORCE_RX_FC BIT(5)
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#define MAC_MCR_FORCE_TX_FC BIT(4)
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#define MAC_MCR_SPEED_1000 BIT(3)
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@@ -461,6 +463,15 @@
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#define MAC_MCR_FORCE_LINK BIT(0)
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#define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE)
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+/* Mac EEE control registers */
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+#define MTK_MAC_EEECR(x) (0x10104 + (x * 0x100))
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+#define MAC_EEE_WAKEUP_TIME_1000 GENMASK(31, 24)
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+#define MAC_EEE_WAKEUP_TIME_100 GENMASK(23, 16)
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+#define MAC_EEE_LPI_TXIDLE_THD GENMASK(15, 8)
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+#define MAC_EEE_CKG_TXIDLE BIT(3)
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+#define MAC_EEE_CKG_RXLPI BIT(2)
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+#define MAC_EEE_LPI_MODE BIT(0)
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+
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/* Mac status registers */
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#define MTK_MAC_MSR(x) (0x10108 + (x * 0x100))
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#define MAC_MSR_EEE1G BIT(7)
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@@ -1321,6 +1332,8 @@ struct mtk_mac {
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int id;
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phy_interface_t interface;
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u8 ppe_idx;
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+ bool tx_lpi_enabled;
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+ u8 txidle_thd_ms;
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int speed;
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struct device_node *of_node;
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struct phylink *phylink;
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