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fa79baf4a6
Copy backport, hack, pending patch and config from 5.15 to 6.1. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
346 lines
11 KiB
Diff
346 lines
11 KiB
Diff
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Wed, 22 Mar 2023 10:15:25 -0700 (PDT)
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From: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= <noltari@gmail.com>
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To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
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krzysztof.kozlowski+dt@linaro.org, p.zabel@pengutronix.de,
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f.fainelli@gmail.com, jonas.gorski@gmail.com,
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william.zhang@broadcom.com, linux-clk@vger.kernel.org,
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Cc: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= <noltari@gmail.com>
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Subject: [PATCH v4 4/4] clk: bcm: Add BCM63268 timer clock and reset driver
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Date: Wed, 22 Mar 2023 18:15:15 +0100
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Message-Id: <20230322171515.120353-5-noltari@gmail.com>
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Add driver for BCM63268 timer clock and reset controller.
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Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
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---
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v4: add changes suggested by Stephen Boyd:
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- Usage of of_device_get_match_data() isn't needed.
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- Use devm_clk_hw_register_gate().
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- Drop clk_hw_unregister_gate().
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v3: add missing <linux/io.h> include to fix build warning
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v2: add changes suggested by Stephen Boyd
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drivers/clk/bcm/Kconfig | 9 ++
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drivers/clk/bcm/Makefile | 1 +
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drivers/clk/bcm/clk-bcm63268-timer.c | 215 +++++++++++++++++++++++++++
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3 files changed, 225 insertions(+)
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create mode 100644 drivers/clk/bcm/clk-bcm63268-timer.c
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--- a/drivers/clk/bcm/Kconfig
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+++ b/drivers/clk/bcm/Kconfig
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@@ -37,6 +37,15 @@ config CLK_BCM_63XX_GATE
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Enable common clock framework support for Broadcom BCM63xx DSL SoCs
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based on the MIPS architecture
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+config CLK_BCM63268_TIMER
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+ bool "Broadcom BCM63268 timer clock and reset support"
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+ depends on BMIPS_GENERIC || COMPILE_TEST
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+ default BMIPS_GENERIC
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+ select RESET_CONTROLLER
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+ help
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+ Enable timer clock and reset support for Broadcom BCM63268 DSL SoCs
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+ based on the MIPS architecture.
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+
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config CLK_BCM_KONA
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bool "Broadcom Kona CCU clock support"
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depends on ARCH_BCM_MOBILE || COMPILE_TEST
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--- a/drivers/clk/bcm/Makefile
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+++ b/drivers/clk/bcm/Makefile
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@@ -1,6 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_CLK_BCM_63XX) += clk-bcm63xx.o
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obj-$(CONFIG_CLK_BCM_63XX_GATE) += clk-bcm63xx-gate.o
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+obj-$(CONFIG_CLK_BCM63268_TIMER) += clk-bcm63268-timer.o
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obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o
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obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
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obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
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--- /dev/null
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+++ b/drivers/clk/bcm/clk-bcm63268-timer.c
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@@ -0,0 +1,215 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * BCM63268 Timer Clock and Reset Controller Driver
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+ *
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+ * Copyright (C) 2023 Álvaro Fernández Rojas <noltari@gmail.com>
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+ */
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+
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+#include <linux/clk-provider.h>
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+#include <linux/delay.h>
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+#include <linux/io.h>
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+#include <linux/of.h>
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+#include <linux/of_device.h>
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+#include <linux/platform_device.h>
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+#include <linux/reset-controller.h>
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+
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+#include <dt-bindings/clock/bcm63268-clock.h>
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+
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+#define BCM63268_TIMER_RESET_SLEEP_MIN_US 10000
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+#define BCM63268_TIMER_RESET_SLEEP_MAX_US 20000
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+
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+struct bcm63268_tclkrst_hw {
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+ void __iomem *regs;
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+ spinlock_t lock;
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+
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+ struct reset_controller_dev rcdev;
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+ struct clk_hw_onecell_data data;
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+};
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+
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+struct bcm63268_tclk_table_entry {
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+ const char * const name;
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+ u8 bit;
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+};
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+
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+static const struct bcm63268_tclk_table_entry bcm63268_timer_clocks[] = {
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+ {
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+ .name = "ephy1",
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+ .bit = BCM63268_TCLK_EPHY1,
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+ }, {
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+ .name = "ephy2",
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+ .bit = BCM63268_TCLK_EPHY2,
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+ }, {
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+ .name = "ephy3",
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+ .bit = BCM63268_TCLK_EPHY3,
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+ }, {
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+ .name = "gphy1",
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+ .bit = BCM63268_TCLK_GPHY1,
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+ }, {
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+ .name = "dsl",
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+ .bit = BCM63268_TCLK_DSL,
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+ }, {
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+ .name = "wakeon_ephy",
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+ .bit = BCM63268_TCLK_WAKEON_EPHY,
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+ }, {
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+ .name = "wakeon_dsl",
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+ .bit = BCM63268_TCLK_WAKEON_DSL,
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+ }, {
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+ .name = "fap1_pll",
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+ .bit = BCM63268_TCLK_FAP1,
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+ }, {
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+ .name = "fap2_pll",
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+ .bit = BCM63268_TCLK_FAP2,
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+ }, {
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+ .name = "uto_50",
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+ .bit = BCM63268_TCLK_UTO_50,
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+ }, {
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+ .name = "uto_extin",
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+ .bit = BCM63268_TCLK_UTO_EXTIN,
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+ }, {
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+ .name = "usb_ref",
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+ .bit = BCM63268_TCLK_USB_REF,
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+ }, {
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+ /* sentinel */
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+ }
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+};
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+
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+static inline struct bcm63268_tclkrst_hw *
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+to_bcm63268_timer_reset(struct reset_controller_dev *rcdev)
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+{
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+ return container_of(rcdev, struct bcm63268_tclkrst_hw, rcdev);
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+}
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+
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+static int bcm63268_timer_reset_update(struct reset_controller_dev *rcdev,
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+ unsigned long id, bool assert)
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+{
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+ struct bcm63268_tclkrst_hw *reset = to_bcm63268_timer_reset(rcdev);
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+ unsigned long flags;
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+ uint32_t val;
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+
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+ spin_lock_irqsave(&reset->lock, flags);
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+ val = __raw_readl(reset->regs);
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+ if (assert)
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+ val &= ~BIT(id);
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+ else
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+ val |= BIT(id);
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+ __raw_writel(val, reset->regs);
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+ spin_unlock_irqrestore(&reset->lock, flags);
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+
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+ return 0;
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+}
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+
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+static int bcm63268_timer_reset_assert(struct reset_controller_dev *rcdev,
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+ unsigned long id)
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+{
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+ return bcm63268_timer_reset_update(rcdev, id, true);
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+}
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+
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+static int bcm63268_timer_reset_deassert(struct reset_controller_dev *rcdev,
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+ unsigned long id)
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+{
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+ return bcm63268_timer_reset_update(rcdev, id, false);
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+}
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+
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+static int bcm63268_timer_reset_reset(struct reset_controller_dev *rcdev,
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+ unsigned long id)
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+{
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+ bcm63268_timer_reset_update(rcdev, id, true);
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+ usleep_range(BCM63268_TIMER_RESET_SLEEP_MIN_US,
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+ BCM63268_TIMER_RESET_SLEEP_MAX_US);
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+
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+ bcm63268_timer_reset_update(rcdev, id, false);
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+ /*
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+ * Ensure component is taken out reset state by sleeping also after
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+ * deasserting the reset. Otherwise, the component may not be ready
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+ * for operation.
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+ */
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+ usleep_range(BCM63268_TIMER_RESET_SLEEP_MIN_US,
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+ BCM63268_TIMER_RESET_SLEEP_MAX_US);
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+
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+ return 0;
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+}
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+
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+static int bcm63268_timer_reset_status(struct reset_controller_dev *rcdev,
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+ unsigned long id)
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+{
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+ struct bcm63268_tclkrst_hw *reset = to_bcm63268_timer_reset(rcdev);
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+
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+ return !(__raw_readl(reset->regs) & BIT(id));
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+}
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+
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+static struct reset_control_ops bcm63268_timer_reset_ops = {
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+ .assert = bcm63268_timer_reset_assert,
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+ .deassert = bcm63268_timer_reset_deassert,
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+ .reset = bcm63268_timer_reset_reset,
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+ .status = bcm63268_timer_reset_status,
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+};
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+
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+static int bcm63268_tclk_probe(struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+ const struct bcm63268_tclk_table_entry *entry;
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+ struct bcm63268_tclkrst_hw *hw;
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+ struct clk_hw *clk;
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+ u8 maxbit = 0;
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+ int i, ret;
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+
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+ for (entry = bcm63268_timer_clocks; entry->name; entry++)
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+ maxbit = max(maxbit, entry->bit);
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+ maxbit++;
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+
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+ hw = devm_kzalloc(&pdev->dev, struct_size(hw, data.hws, maxbit),
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+ GFP_KERNEL);
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+ if (!hw)
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+ return -ENOMEM;
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+
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+ platform_set_drvdata(pdev, hw);
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+
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+ spin_lock_init(&hw->lock);
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+
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+ hw->data.num = maxbit;
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+ for (i = 0; i < maxbit; i++)
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+ hw->data.hws[i] = ERR_PTR(-ENODEV);
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+
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+ hw->regs = devm_platform_ioremap_resource(pdev, 0);
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+ if (IS_ERR(hw->regs))
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+ return PTR_ERR(hw->regs);
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+
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+ for (entry = bcm63268_timer_clocks; entry->name; entry++) {
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+ clk = devm_clk_hw_register_gate(dev, entry->name, NULL, 0,
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+ hw->regs, entry->bit,
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+ CLK_GATE_BIG_ENDIAN,
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+ &hw->lock);
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+ if (IS_ERR(clk))
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+ return PTR_ERR(clk);
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+
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+ hw->data.hws[entry->bit] = clk;
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+ }
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+
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+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
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+ &hw->data);
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+ if (ret)
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+ return ret;
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+
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+ hw->rcdev.of_node = dev->of_node;
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+ hw->rcdev.ops = &bcm63268_timer_reset_ops;
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+
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+ ret = devm_reset_controller_register(dev, &hw->rcdev);
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+ if (ret)
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+ dev_err(dev, "Failed to register reset controller\n");
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+
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+ return 0;
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+}
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+
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+static const struct of_device_id bcm63268_tclk_dt_ids[] = {
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+ { .compatible = "brcm,bcm63268-timer-clocks" },
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+ { /* sentinel */ }
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+};
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+
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+static struct platform_driver bcm63268_tclk = {
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+ .probe = bcm63268_tclk_probe,
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+ .driver = {
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+ .name = "bcm63268-timer-clock",
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+ .of_match_table = bcm63268_tclk_dt_ids,
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+ },
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+};
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+builtin_platform_driver(bcm63268_tclk);
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