mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2025-11-03 14:34:27 -05:00
80 lines
2.1 KiB
Diff
80 lines
2.1 KiB
Diff
--- a/drivers/net/wireless/ath/ath9k/hw.c
|
|
+++ b/drivers/net/wireless/ath/ath9k/hw.c
|
|
@@ -245,6 +245,19 @@ void ath9k_hw_get_channel_centers(struct
|
|
centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
|
|
}
|
|
|
|
+static inline void ath9k_hw_disable_pll_lock_detect(struct ath_hw *ah)
|
|
+{
|
|
+ /* On AR9330 and AR9340 devices, some PHY registers must be
|
|
+ * tuned to gain better stability/performance. These registers
|
|
+ * might be changed while doing wlan reset so the registers must
|
|
+ * be reprogrammed after each reset.
|
|
+ */
|
|
+ REG_CLR_BIT(ah, AR_PHY_USB_CTRL1, BIT(20));
|
|
+ REG_RMW(ah, AR_PHY_USB_CTRL2,
|
|
+ (1 << 21) | (0xf << 22),
|
|
+ (1 << 21) | (0x3 << 22));
|
|
+}
|
|
+
|
|
/******************/
|
|
/* Chip Revisions */
|
|
/******************/
|
|
@@ -1381,6 +1394,9 @@ static bool ath9k_hw_set_reset(struct at
|
|
if (AR_SREV_9100(ah))
|
|
udelay(50);
|
|
|
|
+ if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
|
|
+ ath9k_hw_disable_pll_lock_detect(ah);
|
|
+
|
|
return true;
|
|
}
|
|
|
|
@@ -1480,6 +1496,9 @@ static bool ath9k_hw_chip_reset(struct a
|
|
ar9003_hw_internal_regulator_apply(ah);
|
|
ath9k_hw_init_pll(ah, chan);
|
|
|
|
+ if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
|
|
+ ath9k_hw_disable_pll_lock_detect(ah);
|
|
+
|
|
return true;
|
|
}
|
|
|
|
@@ -1781,8 +1800,14 @@ static int ath9k_hw_do_fastcc(struct ath
|
|
if (AR_SREV_9271(ah))
|
|
ar9002_hw_load_ani_reg(ah, chan);
|
|
|
|
+ if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
|
|
+ ath9k_hw_disable_pll_lock_detect(ah);
|
|
+
|
|
return 0;
|
|
fail:
|
|
+ if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
|
|
+ ath9k_hw_disable_pll_lock_detect(ah);
|
|
+
|
|
return -EINVAL;
|
|
}
|
|
|
|
@@ -2036,6 +2061,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
|
|
ath9k_hw_set_radar_params(ah);
|
|
}
|
|
|
|
+ if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
|
|
+ ath9k_hw_disable_pll_lock_detect(ah);
|
|
+
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(ath9k_hw_reset);
|
|
--- a/drivers/net/wireless/ath/ath9k/phy.h
|
|
+++ b/drivers/net/wireless/ath/ath9k/phy.h
|
|
@@ -48,6 +48,9 @@
|
|
#define AR_PHY_PLL_CONTROL 0x16180
|
|
#define AR_PHY_PLL_MODE 0x16184
|
|
|
|
+#define AR_PHY_USB_CTRL1 0x16c84
|
|
+#define AR_PHY_USB_CTRL2 0x16c88
|
|
+
|
|
enum ath9k_ant_div_comb_lna_conf {
|
|
ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
|
|
ATH_ANT_DIV_COMB_LNA2,
|