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39227de5e5
New revision of Methode eDPU boards uses Marvell 88E6361 switch, so lets backport it from kernel 6.5. Since 5.15 doesnt have phylink_get_caps I had to modify the backport to use the old mv88e6393x_phylink_validate instead. I had to fixup one more instance of port_max_speed_mode as well that is not present in 6.5. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
70 lines
2.5 KiB
Diff
70 lines
2.5 KiB
Diff
From 07120894b24cc3cf2318925baeaaf0893e3312e4 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Alexis=20Lothor=C3=A9?= <alexis.lothore@bootlin.com>
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Date: Mon, 29 May 2023 10:02:43 +0200
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Subject: [PATCH 895/898] net: dsa: mv88e6xxx: add field to specify internal
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phys layout
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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mv88e6xxx currently assumes that switch equipped with internal phys have
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those phys mapped contiguously starting from port 0 (see
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mv88e6xxx_phy_is_internal). However, some switches have internal PHYs but
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NOT starting from port 0. For example 88e6393X, 88E6193X and 88E6191X have
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integrated PHYs available on ports 1 to 8
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To properly support this offset, add a new field to allow specifying an
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internal PHYs layout. If field is not set, default layout is assumed (start
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at port 0)
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Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/dsa/mv88e6xxx/chip.c | 4 +++-
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drivers/net/dsa/mv88e6xxx/chip.h | 5 +++++
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drivers/net/dsa/mv88e6xxx/global2.c | 5 ++++-
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3 files changed, 12 insertions(+), 2 deletions(-)
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--- a/drivers/net/dsa/mv88e6xxx/chip.c
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+++ b/drivers/net/dsa/mv88e6xxx/chip.c
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@@ -461,7 +461,9 @@ restore_link:
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static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
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{
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- return port < chip->info->num_internal_phys;
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+ return port >= chip->info->internal_phys_offset &&
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+ port < chip->info->num_internal_phys +
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+ chip->info->internal_phys_offset;
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}
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static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
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--- a/drivers/net/dsa/mv88e6xxx/chip.h
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+++ b/drivers/net/dsa/mv88e6xxx/chip.h
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@@ -165,6 +165,11 @@ struct mv88e6xxx_info {
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/* Supports PTP */
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bool ptp_support;
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+
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+ /* Internal PHY start index. 0 means that internal PHYs range starts at
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+ * port 0, 1 means internal PHYs range starts at port 1, etc
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+ */
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+ unsigned int internal_phys_offset;
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};
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struct mv88e6xxx_atu_entry {
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--- a/drivers/net/dsa/mv88e6xxx/global2.c
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+++ b/drivers/net/dsa/mv88e6xxx/global2.c
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@@ -1185,8 +1185,11 @@ int mv88e6xxx_g2_irq_mdio_setup(struct m
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struct mii_bus *bus)
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{
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int phy, irq, err, err_phy;
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+ int phy_start = chip->info->internal_phys_offset;
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+ int phy_end = chip->info->internal_phys_offset +
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+ chip->info->num_internal_phys;
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- for (phy = 0; phy < chip->info->num_internal_phys; phy++) {
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+ for (phy = phy_start; phy < phy_end; phy++) {
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irq = irq_find_mapping(chip->g2_irq.domain, phy);
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if (irq < 0) {
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err = irq;
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