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git://git.openwrt.org/openwrt/openwrt.git
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fa8e8d262e
The GW5520 is a small form-factor single-board computer with the following features: * 70x100mm form-factor * IMX6DL 800MHz SoC (IMX6Q optional) * 512MB 32bit DDR3 SDRAM (up to 2GB optional) * 256MB NAND FLASH (up to 2GB optional) * Gateworks System Controller * 2x front-panel Intel i210 GbE adapters with passive PoE support * 2x MiniPCIe sockets with USB support * 2x front-panel USB * 1x rear-panel full-size HDMI connector * 1x front-panel bi-color user LED * 1x front-panel user pushbutton * 1x rear-panel barrel jack for power * 1x Application connector with: * 2x TTL level UARTs * 10x TTL level Digital IO Signed-off-by: Tim Harvey <tharvey@gateworks.com> SVN-Revision: 42148
59 lines
1.9 KiB
Diff
59 lines
1.9 KiB
Diff
This patch allows passing in the gpio output mask used for GPIO0-7 on the
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PLX PCIe bridge. These GPIO's are used for PERST# on the downstream ports.
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Allowing the kernel to override the default configuration allows for keeping
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specific devices held in reset. One important use of this is to allow
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temporarily disabling devices that may request too many resources such as
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an unprogrammed i210 device.
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--- a/arch/arm/mach-imx/mach-imx6q.c
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+++ b/arch/arm/mach-imx/mach-imx6q.c
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@@ -84,6 +84,7 @@ static int ksz9031rn_phy_fixup(struct ph
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* fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
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* as they are used for slots1-7 PERST#
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*/
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+unsigned int ventana_plx_gpio = 0xfe;
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static void ventana_pciesw_early_fixup(struct pci_dev *dev)
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{
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u32 dw;
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@@ -95,19 +96,25 @@ static void ventana_pciesw_early_fixup(s
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return;
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pci_read_config_dword(dev, 0x62c, &dw);
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+ dev_info(&dev->dev, "de-asserting downstream PERST# 0x%04x\n",
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+ ventana_plx_gpio);
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dw |= 0xaaa8; // GPIO1-7 outputs
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pci_write_config_dword(dev, 0x62c, dw);
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-
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- pci_read_config_dword(dev, 0x644, &dw);
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- dw |= 0xfe; // GPIO1-7 output high
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- pci_write_config_dword(dev, 0x644, dw);
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-
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+ pci_write_config_dword(dev, 0x644, ventana_plx_gpio);
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msleep(100);
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup);
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+static int __init setup_ventana_plx_gpio(char *str)
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+{
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+ get_option(&str, &ventana_plx_gpio);
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+
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+ return 0;
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+}
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+early_param("plx_gpio", setup_ventana_plx_gpio);
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+
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static int ar8031_phy_fixup(struct phy_device *dev)
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{
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u16 val;
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@@ -308,7 +315,7 @@ static void __init imx6q_init_irq(void)
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irqchip_init();
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}
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-static const char *imx6q_dt_compat[] __initconst = {
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+static const char *imx6q_dt_compat[] __initdata = {
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"fsl,imx6dl",
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"fsl,imx6q",
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NULL,
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