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e2c3c2280c
A typo in the definition for the OM2P reset button disabled its functionality in OpenWrt. The actual button for these two devices is "1" and not "11". Signed-off-by: Oren Poleg <oren@poleg.org> [sven@open-mesh.org: added a commit subject+message] Signed-off-by: Sven Eckelmann <sven@open-mesh.com> SVN-Revision: 42782
226 lines
6.3 KiB
C
226 lines
6.3 KiB
C
/*
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* OpenMesh OM2P support
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*
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* Copyright (C) 2011 Marek Lindner <marek@open-mesh.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/gpio.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/platform_device.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include <asm/mach-ath79/ath79.h>
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#include "common.h"
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#include "dev-ap9x-pci.h"
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#include "dev-eth.h"
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#include "dev-gpio-buttons.h"
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#include "dev-leds-gpio.h"
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#include "dev-m25p80.h"
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#include "dev-wmac.h"
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#include "machtypes.h"
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#define OM2P_GPIO_LED_POWER 0
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#define OM2P_GPIO_LED_GREEN 13
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#define OM2P_GPIO_LED_RED 14
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#define OM2P_GPIO_LED_YELLOW 15
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#define OM2P_GPIO_LED_LAN 16
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#define OM2P_GPIO_LED_WAN 17
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#define OM2P_GPIO_BTN_RESET 1
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#define OM2P_KEYS_POLL_INTERVAL 20 /* msecs */
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#define OM2P_KEYS_DEBOUNCE_INTERVAL (3 * OM2P_KEYS_POLL_INTERVAL)
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#define OM2P_WAN_PHYMASK BIT(4)
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#define OM2P_LC_GPIO_LED_POWER 1
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#define OM2P_LC_GPIO_LED_GREEN 15
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#define OM2P_LC_GPIO_LED_RED 16
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#define OM2P_LC_GPIO_LED_YELLOW 0
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#define OM2P_LC_GPIO_LED_LAN 13
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#define OM2P_LC_GPIO_LED_WAN 17
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#define OM2P_LC_GPIO_BTN_RESET 12
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static struct flash_platform_data om2p_flash_data = {
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.type = "s25sl12800",
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.name = "ar7240-nor0",
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};
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static struct gpio_led om2p_leds_gpio[] __initdata = {
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{
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.name = "om2p:blue:power",
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.gpio = OM2P_GPIO_LED_POWER,
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.active_low = 1,
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}, {
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.name = "om2p:red:wifi",
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.gpio = OM2P_GPIO_LED_RED,
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.active_low = 1,
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}, {
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.name = "om2p:yellow:wifi",
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.gpio = OM2P_GPIO_LED_YELLOW,
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.active_low = 1,
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}, {
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.name = "om2p:green:wifi",
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.gpio = OM2P_GPIO_LED_GREEN,
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.active_low = 1,
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}, {
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.name = "om2p:blue:lan",
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.gpio = OM2P_GPIO_LED_LAN,
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.active_low = 1,
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}, {
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.name = "om2p:blue:wan",
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.gpio = OM2P_GPIO_LED_WAN,
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.active_low = 1,
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}
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};
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static struct gpio_keys_button om2p_gpio_keys[] __initdata = {
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{
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.desc = "reset",
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.type = EV_KEY,
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.code = KEY_RESTART,
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.debounce_interval = OM2P_KEYS_DEBOUNCE_INTERVAL,
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.gpio = OM2P_GPIO_BTN_RESET,
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.active_low = 1,
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}
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};
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static void __init om2p_setup(void)
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{
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u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000);
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u8 *mac2 = (u8 *)KSEG1ADDR(0x1ffc0000 + ETH_ALEN);
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u8 *ee = (u8 *)KSEG1ADDR(0x1ffc1000);
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ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
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AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
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AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
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AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
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AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
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ath79_register_m25p80(&om2p_flash_data);
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ath79_register_mdio(0, ~OM2P_WAN_PHYMASK);
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ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
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ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
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ath79_register_eth(0);
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ath79_register_eth(1);
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ap91_pci_init(ee, NULL);
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ath79_register_leds_gpio(-1, ARRAY_SIZE(om2p_leds_gpio),
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om2p_leds_gpio);
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ath79_register_gpio_keys_polled(-1, OM2P_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(om2p_gpio_keys),
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om2p_gpio_keys);
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}
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MIPS_MACHINE(ATH79_MACH_OM2P, "OM2P", "OpenMesh OM2P", om2p_setup);
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static struct flash_platform_data om2p_lc_flash_data = {
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.type = "s25sl12800",
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};
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static void __init om2p_lc_setup(void)
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{
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u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000);
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u8 *mac2 = (u8 *)KSEG1ADDR(0x1ffc0000 + ETH_ALEN);
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u8 *art = (u8 *)KSEG1ADDR(0x1ffc1000);
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u32 t;
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ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
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AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
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AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
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AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
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AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
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t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
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t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN;
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ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t);
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ath79_register_m25p80(&om2p_lc_flash_data);
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om2p_leds_gpio[0].gpio = OM2P_LC_GPIO_LED_POWER;
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om2p_leds_gpio[1].gpio = OM2P_LC_GPIO_LED_RED;
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om2p_leds_gpio[2].gpio = OM2P_LC_GPIO_LED_YELLOW;
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om2p_leds_gpio[3].gpio = OM2P_LC_GPIO_LED_GREEN;
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om2p_leds_gpio[4].gpio = OM2P_LC_GPIO_LED_LAN;
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om2p_leds_gpio[5].gpio = OM2P_LC_GPIO_LED_WAN;
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ath79_register_leds_gpio(-1, ARRAY_SIZE(om2p_leds_gpio),
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om2p_leds_gpio);
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om2p_gpio_keys[0].gpio = OM2P_LC_GPIO_BTN_RESET;
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ath79_register_gpio_keys_polled(-1, OM2P_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(om2p_gpio_keys),
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om2p_gpio_keys);
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ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
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ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
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ath79_register_mdio(0, 0x0);
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ath79_register_eth(0);
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ath79_register_eth(1);
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ath79_register_wmac(art, NULL);
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}
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MIPS_MACHINE(ATH79_MACH_OM2P_LC, "OM2P-LC", "OpenMesh OM2P LC", om2p_lc_setup);
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MIPS_MACHINE(ATH79_MACH_OM2Pv2, "OM2Pv2", "OpenMesh OM2Pv2", om2p_lc_setup);
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static void __init om2p_hs_setup(void)
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{
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u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000);
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u8 *mac2 = (u8 *)KSEG1ADDR(0x1ffc0000 + ETH_ALEN);
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u8 *art = (u8 *)KSEG1ADDR(0x1ffc1000);
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/* make lan / wan leds software controllable */
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ath79_gpio_output_select(OM2P_GPIO_LED_LAN, AR934X_GPIO_OUT_GPIO);
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ath79_gpio_output_select(OM2P_GPIO_LED_WAN, AR934X_GPIO_OUT_GPIO);
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/* enable reset button */
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ath79_gpio_output_select(OM2P_GPIO_BTN_RESET, AR934X_GPIO_OUT_GPIO);
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ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
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om2p_leds_gpio[4].gpio = OM2P_GPIO_LED_WAN;
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om2p_leds_gpio[5].gpio = OM2P_GPIO_LED_LAN;
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ath79_register_m25p80(&om2p_lc_flash_data);
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ath79_register_leds_gpio(-1, ARRAY_SIZE(om2p_leds_gpio),
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om2p_leds_gpio);
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ath79_register_gpio_keys_polled(-1, OM2P_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(om2p_gpio_keys),
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om2p_gpio_keys);
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ath79_register_wmac(art, NULL);
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ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
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ath79_register_mdio(1, 0x0);
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ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
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ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
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/* GMAC0 is connected to the PHY0 of the internal switch */
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ath79_switch_data.phy4_mii_en = 1;
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ath79_switch_data.phy_poll_mask = BIT(0);
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
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ath79_eth0_data.phy_mask = BIT(0);
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ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
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ath79_register_eth(0);
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/* GMAC1 is connected to the internal switch */
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ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
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ath79_register_eth(1);
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}
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MIPS_MACHINE(ATH79_MACH_OM2P_HS, "OM2P-HS", "OpenMesh OM2P HS", om2p_hs_setup);
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MIPS_MACHINE(ATH79_MACH_OM2P_HSv2, "OM2P-HSv2", "OpenMesh OM2P HSv2", om2p_hs_setup);
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