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			66 lines
		
	
	
		
			1.8 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			66 lines
		
	
	
		
			1.8 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * (C) Copyright 2010
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|  * Michael Kurz <michi.kurz@googlemail.com>.
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|  *
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|  * See file CREDITS for list of people who contributed to this
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|  * project.
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|  *
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|  * This program is free software; you can redistribute it and/or
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|  * modify it under the terms of the GNU General Public License as
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|  * published by the Free Software Foundation; either version 2 of
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|  * the License, or (at your option) any later version.
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|  *
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|  * This program is distributed in the hope that it will be useful,
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|  * but WITHOUT ANY WARRANTY; without even the implied warranty of
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|  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
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|  * GNU General Public License for more details.
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|  *
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|  * You should have received a copy of the GNU General Public License
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|  * along with this program; if not, write to the Free Software
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|  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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|  * MA 02111-1307 USA
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|  */
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| 
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| #ifndef _AR71XX_GPIO_H
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| #define _AR71XX_GPIO_H
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| 
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| #include <common.h>
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| #include <asm/ar71xx.h>
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| 
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| static inline void ar71xx_setpin(uint8_t pin, uint8_t state)
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| {
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| 	uint32_t reg = readl(KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_OUT));
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| 
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| 	if (state != 0) {
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|        reg |= (1 << pin);
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|    } else {
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|        reg &= ~(1 << pin);
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|    }
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| 
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| 	writel(reg, KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_OUT));
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| 	readl(KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_OUT));
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| }
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| 
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| static inline uint32_t ar71xx_getpin(uint8_t pin)
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| {
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|     uint32_t reg = readl(KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_IN));
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|     return (((reg & (1 << pin)) != 0) ? 1 : 0);
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| }
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| 
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| static inline void ar71xx_setpindir(uint8_t pin, uint8_t direction)
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| {
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| 	uint32_t reg = readl(KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_OE));
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| 
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| 	if (direction != 0) {
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|         reg |= (1 << pin);
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|     } else {
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|         reg &= ~(1 << pin);
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|     }
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| 
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| 	writel(reg, KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_OE));
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| 	readl(KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_OE));
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| }
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| 
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| 
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| #endif /* AR71XX_GPIO_H */
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