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4ed209326b
Siflower SF19A2890 is an SoC with: Dual-core MIPS InterAptiv at 800MHz DDR3 controller One Gigabit Ethernet MAC with RGMII and IPv4 HNAT engine Built-in 2x2 11N + 2x2 11AC WiFi radio USB 2.0 OTG I2C/SPI/GPIO and various other peripherals This PR adds support for SF19A2890 EVB with ethernet support. EVB spec: Memory: DDR3 128M Ethernet: RTL8367RB 5-port gigabit switch Flash: 16M NOR Others: MicroUSB OTG, LED x 1, Reset button x1 The built image can be flashed using u-boot recovery. This target is marked as source-only until support for a commercial router board comes. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
516 lines
12 KiB
C
516 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Driver for Siflower SF19A2890 pinctrl.
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*
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* Based on:
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* Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
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*
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* Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
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*/
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#include <linux/bitmap.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/platform_device.h>
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#define MODULE_NAME "sf19a2890-pinctrl"
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struct sf_pinctrl {
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struct device *dev;
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void __iomem *base;
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struct pinctrl_dev *pctl_dev;
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struct pinctrl_desc pctl_desc;
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struct pinctrl_gpio_range gpio_range;
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};
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#define SF19A28_NUM_GPIOS 49
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#define SF19A28_REG_PC(pin) ((pin) * 0x8)
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#define PC_OEN BIT(7)
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#define PC_ST BIT(6)
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#define PC_IE BIT(5)
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#define PC_PD BIT(4)
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#define PC_PU BIT(3)
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#define PC_DS GENMASK(2, 0)
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#define DRIVE_MIN 6
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#define DRIVE_STEP 3
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#define DRIVE_MAX (7 * DRIVE_STEP)
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#define SF19A28_REG_PMX(pin) ((pin) * 0x8 + 0x4)
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/*
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* FUNC_SW:
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* 0: Override pad output enable with PC_OEN
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* 1: take OEN from GPIO or alternative function
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* FMUX_SEL:
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* 0: Alternative function mode
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* 1: GPIO mode
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*/
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#define PMX_FUNC_SW BIT(3)
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#define PMX_FMUX_SEL BIT(2)
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#define PMX_MODE GENMASK(1, 0)
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static struct pinctrl_pin_desc sf19a2890_gpio_pins[] = {
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PINCTRL_PIN(0, "JTAG_TDO"),
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PINCTRL_PIN(1, "JTAG_TDI"),
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PINCTRL_PIN(2, "JTAG_TMS"),
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PINCTRL_PIN(3, "JTAG_TCK"),
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PINCTRL_PIN(4, "JTAG_RST"),
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PINCTRL_PIN(5, "SPI_TXD"),
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PINCTRL_PIN(6, "SPI_RXD"),
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PINCTRL_PIN(7, "SPI_CLK"),
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PINCTRL_PIN(8, "SPI_CSN"),
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PINCTRL_PIN(9, "UART_TX"),
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PINCTRL_PIN(10, "UART_RX"),
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PINCTRL_PIN(11, "I2C_DAT"),
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PINCTRL_PIN(12, "I2C_CLK"),
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PINCTRL_PIN(13, "RGMII_GTX_CLK"),
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PINCTRL_PIN(14, "RGMII_TXCLK"),
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PINCTRL_PIN(15, "RGMII_TXD0"),
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PINCTRL_PIN(16, "RGMII_TXD1"),
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PINCTRL_PIN(17, "RGMII_TXD2"),
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PINCTRL_PIN(18, "RGMII_TXD3"),
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PINCTRL_PIN(19, "RGMII_TXCTL"),
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PINCTRL_PIN(20, "RGMII_RXCLK"),
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PINCTRL_PIN(21, "RGMII_RXD0"),
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PINCTRL_PIN(22, "RGMII_RXD1"),
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PINCTRL_PIN(23, "RGMII_RXD2"),
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PINCTRL_PIN(24, "RGMII_RXD3"),
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PINCTRL_PIN(25, "RGMII_RXCTL"),
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PINCTRL_PIN(26, "RGMII_COL"),
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PINCTRL_PIN(27, "RGMII_CRS"),
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PINCTRL_PIN(28, "RGMII_MDC"),
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PINCTRL_PIN(29, "RGMII_MDIO"),
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PINCTRL_PIN(30, "HB0_PA_EN"),
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PINCTRL_PIN(31, "HB0_LNA_EN"),
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PINCTRL_PIN(32, "HB0_SW_CTRL0"),
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PINCTRL_PIN(33, "HB0_SW_CTRL1"),
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PINCTRL_PIN(34, "HB1_PA_EN"),
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PINCTRL_PIN(35, "HB1_LNA_EN"),
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PINCTRL_PIN(36, "HB1_SW_CTRL0"),
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PINCTRL_PIN(37, "HB1_SW_CTRL1"),
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PINCTRL_PIN(38, "LB0_PA_EN"),
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PINCTRL_PIN(39, "LB0_LNA_EN"),
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PINCTRL_PIN(40, "LB0_SW_CTRL0"),
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PINCTRL_PIN(41, "LB0_SW_CTRL1"),
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PINCTRL_PIN(42, "LB1_PA_EN"),
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PINCTRL_PIN(43, "LB1_LNA_EN"),
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PINCTRL_PIN(44, "LB1_SW_CTRL0"),
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PINCTRL_PIN(45, "LB1_SW_CTRL1"),
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PINCTRL_PIN(46, "CLK_OUT"),
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PINCTRL_PIN(47, "EXT_CLK_IN"),
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PINCTRL_PIN(48, "DRVVBUS0"),
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};
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static const char * const sf19a2890_gpio_groups[] = {
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"JTAG_TDO",
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"JTAG_TDI",
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"JTAG_TMS",
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"JTAG_TCK",
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"JTAG_RST",
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"SPI_TXD",
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"SPI_RXD",
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"SPI_CLK",
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"SPI_CSN",
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"UART_TX",
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"UART_RX",
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"I2C_DAT",
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"I2C_CLK",
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"RGMII_GTX_CLK",
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"RGMII_TXCLK",
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"RGMII_TXD0",
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"RGMII_TXD1",
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"RGMII_TXD2",
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"RGMII_TXD3",
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"RGMII_TXCTL",
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"RGMII_RXCLK",
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"RGMII_RXD0",
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"RGMII_RXD1",
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"RGMII_RXD2",
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"RGMII_RXD3",
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"RGMII_RXCTL",
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"RGMII_COL",
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"RGMII_CRS",
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"RGMII_MDC",
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"RGMII_MDIO",
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"HB0_PA_EN",
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"HB0_LNA_EN",
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"HB0_SW_CTRL0",
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"HB0_SW_CTRL1",
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"HB1_PA_EN",
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"HB1_LNA_EN",
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"HB1_SW_CTRL0",
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"HB1_SW_CTRL1",
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"LB0_PA_EN",
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"LB0_LNA_EN",
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"LB0_SW_CTRL0",
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"LB0_SW_CTRL1",
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"LB1_PA_EN",
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"LB1_LNA_EN",
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"LB1_SW_CTRL0",
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"LB1_SW_CTRL1",
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"CLK_OUT",
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"EXT_CLK_IN",
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"DRVVBUS0",
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};
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#define SF19A28_FUNC0 0
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#define SF19A28_FUNC1 1
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#define SF19A28_FUNC2 2
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#define SF19A28_FUNC3 3
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#define SF19A28_NUM_FUNCS 4
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static const char * const sf19a2890_functions[] = {
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"func0", "func1", "func2", "func3"
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};
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static inline u32 sf_pinctrl_rd(struct sf_pinctrl *pc, ulong reg)
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{
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return readl(pc->base + reg);
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}
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static inline void sf_pinctrl_wr(struct sf_pinctrl *pc, ulong reg, u32 val)
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{
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writel(val, pc->base + reg);
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}
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static inline void sf_pinctrl_rmw(struct sf_pinctrl *pc, ulong reg, u32 clr,
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u32 set)
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{
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u32 val;
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val = sf_pinctrl_rd(pc, reg);
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val &= ~clr;
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val |= set;
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sf_pinctrl_wr(pc, reg, val);
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}
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static int sf19a2890_pctl_get_groups_count(struct pinctrl_dev *pctldev)
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{
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return SF19A28_NUM_GPIOS;
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}
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static const char *sf19a2890_pctl_get_group_name(struct pinctrl_dev *pctldev,
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unsigned selector)
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{
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return sf19a2890_gpio_groups[selector];
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}
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static int sf19a2890_pctl_get_group_pins(struct pinctrl_dev *pctldev,
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unsigned selector,
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const unsigned **pins,
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unsigned *num_pins)
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{
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*pins = &sf19a2890_gpio_pins[selector].number;
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*num_pins = 1;
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return 0;
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}
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static void sf19a2890_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
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struct seq_file *s, unsigned offset)
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{
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struct sf_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
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u32 conf = sf_pinctrl_rd(pc, SF19A28_REG_PC(offset));
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u32 mux = sf_pinctrl_rd(pc, SF19A28_REG_PMX(offset));
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if (!(mux & PMX_FUNC_SW))
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seq_puts(s, "Forced OE");
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else if (mux & PMX_FMUX_SEL)
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seq_puts(s, "GPIO");
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else
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seq_printf(s, "Func%lu", mux & PMX_MODE);
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seq_puts(s, " |");
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if (!(conf & PC_OEN) && !(mux & PMX_FUNC_SW))
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seq_puts(s, " Output");
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if ((conf & PC_ST))
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seq_puts(s, " Schmitt_Trigger");
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if ((conf & PC_IE))
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seq_puts(s, " Input");
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if ((conf & PC_PD))
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seq_puts(s, " Pull_Down");
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if ((conf & PC_PU))
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seq_puts(s, " Pull_Up");
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seq_printf(s, " Drive: %lu mA",
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DRIVE_MIN + (conf & PC_DS) * DRIVE_STEP);
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}
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static const struct pinctrl_ops sf19a2890_pctl_ops = {
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.get_groups_count = sf19a2890_pctl_get_groups_count,
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.get_group_name = sf19a2890_pctl_get_group_name,
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.get_group_pins = sf19a2890_pctl_get_group_pins,
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.pin_dbg_show = sf19a2890_pctl_pin_dbg_show,
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.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
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.dt_free_map = pinconf_generic_dt_free_map,
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};
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static int sf19a2890_pmx_free(struct pinctrl_dev *pctldev, unsigned offset)
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{
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struct sf_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
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sf_pinctrl_rmw(pc, SF19A28_REG_PC(offset), PC_IE, PC_OEN);
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sf_pinctrl_rmw(pc, SF19A28_REG_PMX(offset), PMX_FUNC_SW, 0);
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return 0;
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}
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static int sf19a2890_pmx_get_functions_count(struct pinctrl_dev *pctldev)
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{
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return SF19A28_NUM_FUNCS;
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}
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static const char *sf19a2890_pmx_get_function_name(struct pinctrl_dev *pctldev,
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unsigned selector)
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{
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return sf19a2890_functions[selector];
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}
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static int sf19a2890_pmx_get_function_groups(struct pinctrl_dev *pctldev,
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unsigned selector,
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const char *const **groups,
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unsigned *const num_groups)
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{
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/* every pin can do every function */
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*groups = sf19a2890_gpio_groups;
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*num_groups = SF19A28_NUM_GPIOS;
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return 0;
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}
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static int sf19a2890_pmx_set(struct pinctrl_dev *pctldev,
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unsigned func_selector, unsigned group_selector)
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{
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struct sf_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
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unsigned pin = group_selector;
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sf_pinctrl_wr(pc, SF19A28_REG_PMX(pin),
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PMX_FUNC_SW | FIELD_PREP(PMX_MODE, func_selector));
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return 0;
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}
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static int sf19a2890_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset)
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{
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struct sf_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
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/* Set to GPIO mode & Let peripheral control OEN */
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sf_pinctrl_wr(pc, SF19A28_REG_PMX(offset), PMX_FUNC_SW | PMX_FMUX_SEL);
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/*
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* Set PC_IE regardless of whether GPIO is in input mode.
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* Otherwise GPIO driver can't read back its status in output mode.
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*/
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sf_pinctrl_rmw(pc, SF19A28_REG_PC(offset), 0, PC_IE);
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return 0;
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}
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static void sf19a2890_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset)
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{
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sf19a2890_pmx_free(pctldev, offset);
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}
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static const struct pinmux_ops sf19a2890_pmx_ops = {
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.free = sf19a2890_pmx_free,
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.get_functions_count = sf19a2890_pmx_get_functions_count,
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.get_function_name = sf19a2890_pmx_get_function_name,
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.get_function_groups = sf19a2890_pmx_get_function_groups,
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.set_mux = sf19a2890_pmx_set,
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.gpio_request_enable = sf19a2890_pmx_gpio_request_enable,
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.gpio_disable_free = sf19a2890_pmx_gpio_disable_free,
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};
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static int sf19a2890_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
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unsigned long *config)
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{
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struct sf_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
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enum pin_config_param param = pinconf_to_config_param(*config);
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u32 arg = 0;
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u32 val = 0;
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if (pin >= SF19A28_NUM_GPIOS)
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return -EINVAL;
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val = sf_pinctrl_rd(pc, SF19A28_REG_PC(pin));
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switch (param) {
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case PIN_CONFIG_INPUT_SCHMITT:
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val &= PC_ST;
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if (val)
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arg = 1;
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break;
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case PIN_CONFIG_INPUT_ENABLE:
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val &= PC_IE;
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if (val)
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arg = 1;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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val &= PC_PD;
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if (val)
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arg = 1;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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val &= PC_PU;
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if (val)
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arg = 1;
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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arg = DRIVE_MIN + (val & PC_DS) * DRIVE_STEP;
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break;
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default:
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return -ENOTSUPP;
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}
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*config = pinconf_to_config_packed(param, arg);
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return 0;
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}
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static int sf19a2890_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
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unsigned long *configs, unsigned num_configs)
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{
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struct sf_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
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enum pin_config_param param;
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u32 arg, val;
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int i;
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val = sf_pinctrl_rd(pc, SF19A28_REG_PC(pin));
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if (pin >= SF19A28_NUM_GPIOS)
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return -EINVAL;
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for (i = 0; i < num_configs; i++) {
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param = pinconf_to_config_param(configs[i]);
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arg = pinconf_to_config_argument(configs[i]);
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switch (param) {
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case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
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if (arg)
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val |= PC_ST;
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else
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val &= ~PC_ST;
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break;
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case PIN_CONFIG_INPUT_ENABLE:
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if (arg)
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val |= PC_IE;
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else
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val &= ~PC_IE;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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if (arg) {
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val |= PC_PD;
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val &= ~PC_PU;
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} else {
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val &= ~PC_PD;
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}
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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if (arg) {
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val |= PC_PU;
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val &= ~PC_PD;
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} else {
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val &= ~PC_PU;
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}
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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val &= ~PC_DS;
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if (arg > DRIVE_MAX)
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val |= PC_DS;
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else if (arg > DRIVE_MIN)
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val |= FIELD_PREP(PC_DS, (arg - DRIVE_MIN) /
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DRIVE_STEP);
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break;
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default:
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break;
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}
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sf_pinctrl_wr(pc, SF19A28_REG_PC(pin), val);
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}
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return 0;
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}
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static const struct pinconf_ops sf19a2890_pinconf_ops = {
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.is_generic = true,
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.pin_config_get = sf19a2890_pinconf_get,
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.pin_config_set = sf19a2890_pinconf_set,
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};
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static const struct pinctrl_desc sf19a2890_pinctrl_desc = {
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.name = MODULE_NAME,
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.pins = sf19a2890_gpio_pins,
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.npins = SF19A28_NUM_GPIOS,
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.pctlops = &sf19a2890_pctl_ops,
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.pmxops = &sf19a2890_pmx_ops,
|
|
.confops = &sf19a2890_pinconf_ops,
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
static const struct pinctrl_gpio_range sf_pinctrl_gpio_range = {
|
|
.name = MODULE_NAME,
|
|
.npins = SF19A28_NUM_GPIOS,
|
|
};
|
|
|
|
static const struct of_device_id sf_pinctrl_match[] = {
|
|
{ .compatible = "siflower,sf19a2890-pinctrl" },
|
|
{}
|
|
};
|
|
|
|
static int sf_pinctrl_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct sf_pinctrl *pc;
|
|
|
|
pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
|
|
if (!pc)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, pc);
|
|
pc->dev = dev;
|
|
|
|
pc->base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(pc->base))
|
|
return PTR_ERR(pc->base);
|
|
|
|
pc->pctl_desc = sf19a2890_pinctrl_desc;
|
|
pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
|
|
if (IS_ERR(pc->pctl_dev))
|
|
return PTR_ERR(pc->pctl_dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver sf_pinctrl_driver = {
|
|
.probe = sf_pinctrl_probe,
|
|
.driver = {
|
|
.name = MODULE_NAME,
|
|
.of_match_table = sf_pinctrl_match,
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
};
|
|
module_platform_driver(sf_pinctrl_driver);
|
|
|
|
MODULE_AUTHOR("Chuanhong Guo <gch981213@gmail.com>");
|
|
MODULE_DESCRIPTION("Siflower SF19A2890 pinctrl driver");
|
|
MODULE_LICENSE("GPL");
|