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080691d7b1
Backport Aardvark PCIe controller driver changes that fix MSI support, that were recently sent to the linux-pci mailing list [1]. These changes fix MSI and MSI-X support for this PCIe controller, which, among other things, make it possible to use NVMe drives with this PCIe controllers. [1] https://lore.kernel.org/linux-pci/20220110015018.26359-1-kabel@kernel.org/ Signed-off-by: Marek Behún <kabel@kernel.org>
78 lines
2.8 KiB
Diff
78 lines
2.8 KiB
Diff
From bb03b126ea6c9e57177b537dd022246fa5dbef16 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
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Date: Fri, 12 Feb 2021 16:24:07 +0100
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Subject: [PATCH] PCI: aardvark: Fix support for MSI interrupts
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Aardvark hardware supports Multi-MSI and MSI_FLAG_MULTI_PCI_MSI is already
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set for the MSI chip. But when allocating MSI interrupt numbers for
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Multi-MSI, the numbers need to be properly aligned, otherwise endpoint
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devices send MSI interrupt with incorrect numbers.
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Fix this issue by using function bitmap_find_free_region() instead of
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bitmap_find_next_zero_area().
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To ensure that aligned MSI interrupt numbers are used by endpoint devices,
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we cannot use Linux virtual irq numbers (as they are random and not
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properly aligned). Instead we need to use the aligned hwirq numbers.
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This change fixes receiving MSI interrupts on Armada 3720 boards and
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allows using NVMe disks which use Multi-MSI feature with 3 interrupts.
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Without this NVMe disks freeze booting as linux nvme-core.c is waiting
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60s for an interrupt.
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Signed-off-by: Pali Rohár <pali@kernel.org>
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Signed-off-by: Marek Behún <kabel@kernel.org>
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---
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drivers/pci/controller/pci-aardvark.c | 16 ++++++----------
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1 file changed, 6 insertions(+), 10 deletions(-)
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diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
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index 1c6980a78975..e68773527171 100644
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--- a/drivers/pci/controller/pci-aardvark.c
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+++ b/drivers/pci/controller/pci-aardvark.c
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@@ -1187,7 +1187,7 @@ static void advk_msi_irq_compose_msi_msg(struct irq_data *data,
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msg->address_lo = lower_32_bits(msi_msg);
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msg->address_hi = upper_32_bits(msi_msg);
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- msg->data = data->irq;
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+ msg->data = data->hwirq;
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}
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static int advk_msi_set_affinity(struct irq_data *irq_data,
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@@ -1204,15 +1204,11 @@ static int advk_msi_irq_domain_alloc(struct irq_domain *domain,
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int hwirq, i;
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mutex_lock(&pcie->msi_used_lock);
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- hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM,
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- 0, nr_irqs, 0);
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- if (hwirq >= MSI_IRQ_NUM) {
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- mutex_unlock(&pcie->msi_used_lock);
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- return -ENOSPC;
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- }
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-
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- bitmap_set(pcie->msi_used, hwirq, nr_irqs);
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+ hwirq = bitmap_find_free_region(pcie->msi_used, MSI_IRQ_NUM,
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+ order_base_2(nr_irqs));
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mutex_unlock(&pcie->msi_used_lock);
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+ if (hwirq < 0)
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+ return -ENOSPC;
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for (i = 0; i < nr_irqs; i++)
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irq_domain_set_info(domain, virq + i, hwirq + i,
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@@ -1230,7 +1226,7 @@ static void advk_msi_irq_domain_free(struct irq_domain *domain,
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struct advk_pcie *pcie = domain->host_data;
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mutex_lock(&pcie->msi_used_lock);
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- bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs);
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+ bitmap_release_region(pcie->msi_used, d->hwirq, order_base_2(nr_irqs));
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mutex_unlock(&pcie->msi_used_lock);
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}
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--
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2.34.1
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