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9e5b0cc19c
Sync the patches with those sent upstream for v3.12. Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 37778
630 lines
12 KiB
Diff
630 lines
12 KiB
Diff
From 5845a3aa53cf42893db05662aa9bb91387949ff6 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Mon, 12 Aug 2013 18:11:33 +0200
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Subject: [PATCH 22/25] MIPS: ralink: update dts files
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Add the devicetree nodes needed to make the newly merged drivers work.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/ralink/dts/mt7620a.dtsi | 135 +++++++++++++++++++++++
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arch/mips/ralink/dts/rt3050.dtsi | 156 ++++++++++++++++++++++++++
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arch/mips/ralink/dts/rt3883.dtsi | 219 +++++++++++++++++++++++++++++++++++++
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3 files changed, 510 insertions(+)
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--- a/arch/mips/ralink/dts/mt7620a.dtsi
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+++ b/arch/mips/ralink/dts/mt7620a.dtsi
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@@ -29,10 +29,32 @@
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reg = <0x0 0x100>;
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};
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+ timer@100 {
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+ compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer";
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+ reg = <0x100 0x20>;
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <1>;
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+ };
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+
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+ watchdog@120 {
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+ compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt";
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+ reg = <0x120 0x10>;
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+
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+ resets = <&rstctrl 8>;
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+ reset-names = "wdt";
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <1>;
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+ };
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+
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intc: intc@200 {
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compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
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reg = <0x200 0x100>;
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+ resets = <&rstctrl 19>;
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+ reset-names = "intc";
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+
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interrupt-controller;
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#interrupt-cells = <1>;
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@@ -43,16 +65,129 @@
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memc@300 {
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compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
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reg = <0x300 0x100>;
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+
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+ resets = <&rstctrl 20>;
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+ reset-names = "mc";
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <3>;
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+ };
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+
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+ uart@500 {
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+ compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
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+ reg = <0x500 0x100>;
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+
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+ resets = <&rstctrl 12>;
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+ reset-names = "uart";
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <5>;
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+
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+ reg-shift = <2>;
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+
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+ status = "disabled";
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+ };
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+
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+ gpio0: gpio@600 {
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+ compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
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+ reg = <0x600 0x34>;
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+
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+ resets = <&rstctrl 13>;
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+ reset-names = "pio";
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <6>;
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+
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+
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+ ralink,gpio-base = <0>;
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+ ralink,num-gpios = <24>;
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+ ralink,register-map = [ 00 04 08 0c
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+ 20 24 28 2c
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+ 30 34 ];
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+
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+ status = "disabled";
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+ };
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+
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+ gpio1: gpio@638 {
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+ compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
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+ reg = <0x638 0x24>;
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <6>;
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+
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+
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+ ralink,gpio-base = <24>;
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+ ralink,num-gpios = <16>;
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+ ralink,register-map = [ 00 04 08 0c
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+ 10 14 18 1c
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+ 20 24 ];
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+
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+ status = "disabled";
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+ };
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+
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+ gpio2: gpio@660 {
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+ compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
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+ reg = <0x660 0x24>;
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <6>;
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+
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+
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+ ralink,gpio-base = <40>;
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+ ralink,num-gpios = <32>;
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+ ralink,register-map = [ 00 04 08 0c
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+ 10 14 18 1c
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+ 20 24 ];
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+
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+ status = "disabled";
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+ };
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+
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+ spi@b00 {
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+ compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
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+ reg = <0xb00 0x100>;
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+
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+ resets = <&rstctrl 18>;
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+ reset-names = "spi";
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+
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ status = "disabled";
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};
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uartlite@c00 {
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compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
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reg = <0xc00 0x100>;
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+ resets = <&rstctrl 19>;
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+ reset-names = "uartl";
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+
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interrupt-parent = <&intc>;
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interrupts = <12>;
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reg-shift = <2>;
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};
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+
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+ systick@d00 {
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+ compatible = "ralink,mt7620a-systick", "ralink,cevt-systick";
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+ reg = <0xd00 0x10>;
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+
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+ resets = <&rstctrl 28>;
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+ reset-names = "intc";
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+
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+ interrupt-parent = <&cpuintc>;
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+ interrupts = <7>;
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+ };
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+ };
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+
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+ rstctrl: rstctrl {
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+ compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
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+ #reset-cells = <1>;
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};
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};
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--- a/arch/mips/ralink/dts/rt3050.dtsi
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+++ b/arch/mips/ralink/dts/rt3050.dtsi
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@@ -9,6 +9,10 @@
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};
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};
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+ chosen {
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+ bootargs = "console=ttyS0,57600";
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+ };
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+
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cpuintc: cpuintc@0 {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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@@ -29,10 +33,32 @@
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reg = <0x0 0x100>;
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};
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+ timer@100 {
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+ compatible = "ralink,rt3052-timer", "ralink,rt2880-timer";
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+ reg = <0x100 0x20>;
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <1>;
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+ };
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+
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+ watchdog@120 {
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+ compatible = "ralink,rt3052-wdt", "ralink,rt2880-wdt";
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+ reg = <0x120 0x10>;
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+
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+ resets = <&rstctrl 8>;
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+ reset-names = "wdt";
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <1>;
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+ };
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+
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intc: intc@200 {
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compatible = "ralink,rt3052-intc", "ralink,rt2880-intc";
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reg = <0x200 0x100>;
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+ resets = <&rstctrl 19>;
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+ reset-names = "intc";
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+
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interrupt-controller;
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#interrupt-cells = <1>;
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@@ -43,17 +69,144 @@
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memc@300 {
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compatible = "ralink,rt3052-memc", "ralink,rt3050-memc";
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reg = <0x300 0x100>;
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+
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+ resets = <&rstctrl 20>;
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+ reset-names = "mc";
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <3>;
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+ };
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+
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+ uart@500 {
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+ compatible = "ralink,rt5350-uart", "ralink,rt2880-uart", "ns16550a";
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+ reg = <0x500 0x100>;
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+
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+ resets = <&rstctrl 12>;
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+ reset-names = "uart";
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <5>;
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+
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+ reg-shift = <2>;
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+
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+ status = "disabled";
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+ };
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+
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+ gpio0: gpio@600 {
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+ compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
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+ reg = <0x600 0x34>;
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+
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+
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+ ralink,gpio-base = <0>;
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+ ralink,num-gpios = <24>;
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+ ralink,register-map = [ 00 04 08 0c
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+ 20 24 28 2c
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+ 30 34 ];
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+
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+ resets = <&rstctrl 13>;
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+ reset-names = "pio";
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <6>;
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+
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+ status = "disabled";
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+ };
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+
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+ gpio1: gpio@638 {
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+ compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
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+ reg = <0x638 0x24>;
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+
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+
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+ ralink,gpio-base = <24>;
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+ ralink,num-gpios = <16>;
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+ ralink,register-map = [ 00 04 08 0c
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+ 10 14 18 1c
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+ 20 24 ];
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+
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+ status = "disabled";
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+ };
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+
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+ gpio2: gpio@660 {
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+ compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
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+ reg = <0x660 0x24>;
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+
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+
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+ ralink,gpio-base = <40>;
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+ ralink,num-gpios = <12>;
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+ ralink,register-map = [ 00 04 08 0c
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+ 10 14 18 1c
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+ 20 24 ];
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+
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+ status = "disabled";
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+ };
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+
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+ spi@b00 {
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+ compatible = "ralink,rt3050-spi", "ralink,rt2880-spi";
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+ reg = <0xb00 0x100>;
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+
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+ resets = <&rstctrl 18>;
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+ reset-names = "spi";
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+
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ status = "disabled";
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};
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uartlite@c00 {
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compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
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reg = <0xc00 0x100>;
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+ resets = <&rstctrl 19>;
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+ reset-names = "uartl";
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+
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interrupt-parent = <&intc>;
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interrupts = <12>;
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reg-shift = <2>;
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};
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+
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+ };
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+
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+ rstctrl: rstctrl {
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+ compatible = "ralink,rt3050-reset", "ralink,rt2880-reset";
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+ #reset-cells = <1>;
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+ };
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+
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+ ethernet@10100000 {
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+ compatible = "ralink,rt3050-eth";
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+ reg = <0x10100000 10000>;
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+
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+ interrupt-parent = <&cpuintc>;
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+ interrupts = <5>;
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+
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+ status = "disabled";
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+ };
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+
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+ esw@10110000 {
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+ compatible = "ralink,rt3050-esw";
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+ reg = <0x10110000 8000>;
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <17>;
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+
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+ status = "disabled";
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+ };
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+
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+ wmac@10180000 {
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+ compatible = "ralink,rt3050-wmac", "ralink,rt2880-wmac";
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+ reg = <0x10180000 40000>;
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+
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+ interrupt-parent = <&cpuintc>;
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+ interrupts = <6>;
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+
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+ status = "disabled";
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};
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usb@101c0000 {
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@@ -63,6 +216,9 @@
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interrupt-parent = <&intc>;
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interrupts = <18>;
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+ resets = <&rstctrl 22>;
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+ reset-names = "otg";
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+
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status = "disabled";
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};
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};
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--- a/arch/mips/ralink/dts/rt3883.dtsi
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+++ b/arch/mips/ralink/dts/rt3883.dtsi
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@@ -29,10 +29,32 @@
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reg = <0x0 0x100>;
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};
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+ timer@100 {
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+ compatible = "ralink,rt3883-timer", "ralink,rt2880-timer";
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+ reg = <0x100 0x20>;
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <1>;
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+ };
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+
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+ watchdog@120 {
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+ compatible = "ralink,rt3883-wdt", "ralink,rt2880-wdt";
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+ reg = <0x120 0x10>;
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+
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+ resets = <&rstctrl 8>;
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+ reset-names = "wdt";
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <1>;
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+ };
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+
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intc: intc@200 {
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compatible = "ralink,rt3883-intc", "ralink,rt2880-intc";
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reg = <0x200 0x100>;
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+ resets = <&rstctrl 19>;
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+ reset-names = "intc";
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+
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interrupt-controller;
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#interrupt-cells = <1>;
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@@ -43,16 +65,213 @@
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memc@300 {
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compatible = "ralink,rt3883-memc", "ralink,rt3050-memc";
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reg = <0x300 0x100>;
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+
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+ resets = <&rstctrl 20>;
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+ reset-names = "mc";
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <3>;
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+ };
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+
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+ uart@500 {
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+ compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
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+ reg = <0x500 0x100>;
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+
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+ resets = <&rstctrl 12>;
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+ reset-names = "uart";
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <5>;
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+
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+ reg-shift = <2>;
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+
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+ status = "disabled";
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+ };
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+
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+ gpio0: gpio@600 {
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+ compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
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+ reg = <0x600 0x34>;
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+
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+ resets = <&rstctrl 13>;
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+ reset-names = "pio";
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <6>;
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+
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+
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+ ralink,gpio-base = <0>;
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+ ralink,num-gpios = <24>;
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+ ralink,register-map = [ 00 04 08 0c
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+ 20 24 28 2c
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+ 30 34 ];
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+
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+ status = "disabled";
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+ };
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+
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+ gpio1: gpio@638 {
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+ compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
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+ reg = <0x638 0x24>;
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+
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+
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+ ralink,gpio-base = <24>;
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+ ralink,num-gpios = <16>;
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+ ralink,register-map = [ 00 04 08 0c
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+ 10 14 18 1c
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+ 20 24 ];
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+
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+ status = "disabled";
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+ };
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+
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+ gpio2: gpio@660 {
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+ compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
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+ reg = <0x660 0x24>;
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+
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+
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+ ralink,gpio-base = <40>;
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+ ralink,num-gpios = <32>;
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+ ralink,register-map = [ 00 04 08 0c
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+ 10 14 18 1c
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+ 20 24 ];
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+
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+ status = "disabled";
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+ };
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+
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+ gpio3: gpio@688 {
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+ compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
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+ reg = <0x688 0x24>;
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+
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+
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+ ralink,gpio-base = <72>;
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+ ralink,num-gpios = <24>;
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+ ralink,register-map = [ 00 04 08 0c
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+ 10 14 18 1c
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+ 20 24 ];
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+
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+ status = "disabled";
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+ };
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+
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+ spi0: spi@b00 {
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+ compatible = "ralink,rt3883-spi", "ralink,rt2880-spi";
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+ reg = <0xb00 0x100>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ resets = <&rstctrl 18>;
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+ reset-names = "spi";
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+
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+ status = "disabled";
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};
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|
|
uartlite@c00 {
|
|
compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
|
|
reg = <0xc00 0x100>;
|
|
|
|
+ resets = <&rstctrl 19>;
|
|
+ reset-names = "uartl";
|
|
+
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <12>;
|
|
|
|
reg-shift = <2>;
|
|
};
|
|
};
|
|
+
|
|
+ rstctrl: rstctrl {
|
|
+ compatible = "ralink,rt3883-reset", "ralink,rt2880-reset";
|
|
+ #reset-cells = <1>;
|
|
+ };
|
|
+
|
|
+ pci@10140000 {
|
|
+ compatible = "ralink,rt3883-pci";
|
|
+ reg = <0x10140000 0x20000>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges; /* direct mapping */
|
|
+
|
|
+ status = "disabled";
|
|
+
|
|
+ pciintc: interrupt-controller {
|
|
+ interrupt-controller;
|
|
+ #address-cells = <0>;
|
|
+ #interrupt-cells = <1>;
|
|
+
|
|
+ interrupt-parent = <&cpuintc>;
|
|
+ interrupts = <4>;
|
|
+ };
|
|
+
|
|
+ host-bridge {
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ #interrupt-cells = <1>;
|
|
+
|
|
+ device_type = "pci";
|
|
+
|
|
+ bus-range = <0 255>;
|
|
+ ranges = <
|
|
+ 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
|
|
+ 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
|
|
+ >;
|
|
+
|
|
+ interrupt-map-mask = <0xf800 0 0 7>;
|
|
+ interrupt-map = <
|
|
+ /* IDSEL 17 */
|
|
+ 0x8800 0 0 1 &pciintc 18
|
|
+ 0x8800 0 0 2 &pciintc 18
|
|
+ 0x8800 0 0 3 &pciintc 18
|
|
+ 0x8800 0 0 4 &pciintc 18
|
|
+ /* IDSEL 18 */
|
|
+ 0x9000 0 0 1 &pciintc 19
|
|
+ 0x9000 0 0 2 &pciintc 19
|
|
+ 0x9000 0 0 3 &pciintc 19
|
|
+ 0x9000 0 0 4 &pciintc 19
|
|
+ >;
|
|
+
|
|
+ pci-bridge@1 {
|
|
+ reg = <0x0800 0 0 0 0>;
|
|
+ device_type = "pci";
|
|
+ #interrupt-cells = <1>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+
|
|
+ status = "disabled";
|
|
+
|
|
+ ralink,pci-slot = <1>;
|
|
+
|
|
+ interrupt-map-mask = <0x0 0 0 0>;
|
|
+ interrupt-map = <0x0 0 0 0 &pciintc 20>;
|
|
+ };
|
|
+
|
|
+ pci-slot@17 {
|
|
+ reg = <0x8800 0 0 0 0>;
|
|
+ device_type = "pci";
|
|
+ #interrupt-cells = <1>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+
|
|
+ ralink,pci-slot = <17>;
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pci-slot@18 {
|
|
+ reg = <0x9000 0 0 0 0>;
|
|
+ device_type = "pci";
|
|
+ #interrupt-cells = <1>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+
|
|
+ ralink,pci-slot = <18>;
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
};
|