mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2025-11-03 22:44:27 -05:00
2fc3680dd0
Refresh patches for all targets supporting 4.1 and not marked broken. Compile-tested on all targets using 4.1 and not marked broken. Changes to generic/610-netfilter_match_bypass_default_checks.patch based on84d489f64f. Changes to generic/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch based ona90ee92337. Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
717 lines
23 KiB
Diff
717 lines
23 KiB
Diff
--- a/drivers/bcma/driver_chipcommon.c
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+++ b/drivers/bcma/driver_chipcommon.c
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@@ -15,6 +15,8 @@
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#include <linux/platform_device.h>
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#include <linux/bcma/bcma.h>
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+static void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
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+
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static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
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u32 mask, u32 value)
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{
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@@ -113,8 +115,37 @@ int bcma_chipco_watchdog_register(struct
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return 0;
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}
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+static void bcma_core_chipcommon_flash_detect(struct bcma_drv_cc *cc)
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+{
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+ struct bcma_bus *bus = cc->core->bus;
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+
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+ switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
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+ case BCMA_CC_FLASHT_STSER:
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+ case BCMA_CC_FLASHT_ATSER:
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+ bcma_debug(bus, "Found serial flash\n");
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+ bcma_sflash_init(cc);
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+ break;
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+ case BCMA_CC_FLASHT_PARA:
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+ bcma_debug(bus, "Found parallel flash\n");
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+ bcma_pflash_init(cc);
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+ break;
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+ default:
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+ bcma_err(bus, "Flash type not supported\n");
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+ }
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+
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+ if (cc->core->id.rev == 38 ||
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+ bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
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+ if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
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+ bcma_debug(bus, "Found NAND flash\n");
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+ bcma_nflash_init(cc);
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+ }
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+ }
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+}
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+
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void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
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{
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+ struct bcma_bus *bus = cc->core->bus;
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+
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if (cc->early_setup_done)
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return;
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@@ -129,6 +160,12 @@ void bcma_core_chipcommon_early_init(str
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if (cc->capabilities & BCMA_CC_CAP_PMU)
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bcma_pmu_early_init(cc);
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+ if (IS_BUILTIN(CONFIG_BCM47XX) && bus->hosttype == BCMA_HOSTTYPE_SOC)
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+ bcma_chipco_serial_init(cc);
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+
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+ if (bus->hosttype == BCMA_HOSTTYPE_SOC)
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+ bcma_core_chipcommon_flash_detect(cc);
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+
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cc->early_setup_done = true;
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}
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@@ -185,11 +222,12 @@ u32 bcma_chipco_watchdog_timer_set(struc
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ticks = 2;
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else if (ticks > maxt)
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ticks = maxt;
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- bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
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} else {
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struct bcma_bus *bus = cc->core->bus;
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if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4707 &&
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+ bus->chipinfo.id != BCMA_CHIP_ID_BCM47094 &&
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bus->chipinfo.id != BCMA_CHIP_ID_BCM53018)
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bcma_core_set_clockmode(cc->core,
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ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC);
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@@ -314,9 +352,9 @@ u32 bcma_chipco_gpio_pulldown(struct bcm
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return res;
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}
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-#ifdef CONFIG_BCMA_DRIVER_MIPS
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-void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
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+static void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
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{
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+#if IS_BUILTIN(CONFIG_BCM47XX)
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unsigned int irq;
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u32 baud_base;
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u32 i;
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@@ -358,5 +396,5 @@ void bcma_chipco_serial_init(struct bcma
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ports[i].baud_base = baud_base;
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ports[i].reg_shift = 0;
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}
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+#endif /* CONFIG_BCM47XX */
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}
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-#endif /* CONFIG_BCMA_DRIVER_MIPS */
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--- a/drivers/bcma/driver_chipcommon_pmu.c
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+++ b/drivers/bcma/driver_chipcommon_pmu.c
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@@ -15,44 +15,44 @@
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u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
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{
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- bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
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- bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
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- return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
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+ bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
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+ return bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
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}
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EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
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void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
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{
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- bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
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- bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
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- bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
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+ bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value);
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}
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EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);
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void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
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u32 set)
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{
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- bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
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- bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
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- bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
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+ bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
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+ bcma_pmu_maskset32(cc, BCMA_CC_PMU_PLLCTL_DATA, mask, set);
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}
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EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);
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void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
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u32 offset, u32 mask, u32 set)
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{
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- bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
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- bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
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- bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_CHIPCTL_ADDR, offset);
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+ bcma_pmu_read32(cc, BCMA_CC_PMU_CHIPCTL_ADDR);
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+ bcma_pmu_maskset32(cc, BCMA_CC_PMU_CHIPCTL_DATA, mask, set);
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}
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EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);
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void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
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u32 set)
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{
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- bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);
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- bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);
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- bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_REGCTL_ADDR, offset);
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+ bcma_pmu_read32(cc, BCMA_CC_PMU_REGCTL_ADDR);
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+ bcma_pmu_maskset32(cc, BCMA_CC_PMU_REGCTL_DATA, mask, set);
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}
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EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
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@@ -60,18 +60,18 @@ static u32 bcma_pmu_xtalfreq(struct bcma
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{
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u32 ilp_ctl, alp_hz;
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- if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
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+ if (!(bcma_pmu_read32(cc, BCMA_CC_PMU_STAT) &
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BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
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return 0;
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- bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
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- BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
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+ BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
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usleep_range(1000, 2000);
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- ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
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+ ilp_ctl = bcma_pmu_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
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ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
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- bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
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alp_hz = ilp_ctl * 32768 / 4;
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return (alp_hz + 50000) / 100000 * 100;
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@@ -127,8 +127,8 @@ static void bcma_pmu2_pll_init0(struct b
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mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
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BCMA_RES_4314_MACPHY_CLK_AVAIL);
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- bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
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- bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
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+ bcma_pmu_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
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+ bcma_pmu_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
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bcma_wait_value(cc->core, BCMA_CLKCTLST,
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BCMA_CLKCTLST_HAVEHT, 0, 20000);
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break;
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@@ -140,7 +140,7 @@ static void bcma_pmu2_pll_init0(struct b
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/* Flush */
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if (cc->pmu.rev >= 2)
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- bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
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+ bcma_pmu_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
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/* TODO: Do we need to update OTP? */
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}
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@@ -195,9 +195,9 @@ static void bcma_pmu_resources_init(stru
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/* Set the resource masks. */
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if (min_msk)
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- bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
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if (max_msk)
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- bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
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/*
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* Add some delay; allow resources to come up and settle.
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@@ -269,23 +269,33 @@ static void bcma_pmu_workarounds(struct
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void bcma_pmu_early_init(struct bcma_drv_cc *cc)
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{
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+ struct bcma_bus *bus = cc->core->bus;
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u32 pmucap;
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- pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
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+ if (cc->core->id.rev >= 35 &&
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+ cc->capabilities_ext & BCMA_CC_CAP_EXT_AOB_PRESENT) {
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+ cc->pmu.core = bcma_find_core(bus, BCMA_CORE_PMU);
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+ if (!cc->pmu.core)
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+ bcma_warn(bus, "Couldn't find expected PMU core");
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+ }
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+ if (!cc->pmu.core)
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+ cc->pmu.core = cc->core;
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+
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+ pmucap = bcma_pmu_read32(cc, BCMA_CC_PMU_CAP);
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cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
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- bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
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- cc->pmu.rev, pmucap);
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+ bcma_debug(bus, "Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
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+ pmucap);
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}
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void bcma_pmu_init(struct bcma_drv_cc *cc)
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{
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if (cc->pmu.rev == 1)
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- bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
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- ~BCMA_CC_PMU_CTL_NOILPONW);
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+ bcma_pmu_mask32(cc, BCMA_CC_PMU_CTL,
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+ ~BCMA_CC_PMU_CTL_NOILPONW);
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else
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- bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
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- BCMA_CC_PMU_CTL_NOILPONW);
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+ bcma_pmu_set32(cc, BCMA_CC_PMU_CTL,
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+ BCMA_CC_PMU_CTL_NOILPONW);
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bcma_pmu_pll_init(cc);
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bcma_pmu_resources_init(cc);
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@@ -472,8 +482,8 @@ u32 bcma_pmu_get_cpu_clock(struct bcma_d
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static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
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u32 value)
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{
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- bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
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- bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value);
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}
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void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
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@@ -497,20 +507,20 @@ void bcma_pmu_spuravoid_pllupdate(struct
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bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
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/* RMW only the P1 divider */
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- bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR,
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BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
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- tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
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+ tmp = bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
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tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
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tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
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- bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp);
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/* RMW only the int feedback divider */
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- bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR,
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BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
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- tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
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+ tmp = bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
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tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
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tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
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- bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp);
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tmp = BCMA_CC_PMU_CTL_PLL_UPD;
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break;
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@@ -646,7 +656,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
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break;
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}
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- tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
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- bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
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+ tmp |= bcma_pmu_read32(cc, BCMA_CC_PMU_CTL);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_CTL, tmp);
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}
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EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
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--- a/drivers/bcma/driver_chipcommon_sflash.c
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+++ b/drivers/bcma/driver_chipcommon_sflash.c
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@@ -38,6 +38,7 @@ static const struct bcma_sflash_tbl_e bc
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{ "M25P32", 0x15, 0x10000, 64, },
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{ "M25P64", 0x16, 0x10000, 128, },
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{ "M25FL128", 0x17, 0x10000, 256, },
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+ { "MX25L25635F", 0x18, 0x10000, 512, },
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{ NULL },
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};
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--- a/drivers/bcma/scan.c
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+++ b/drivers/bcma/scan.c
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@@ -98,6 +98,9 @@ static const struct bcma_device_id_name
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{ BCMA_CORE_SHIM, "SHIM" },
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{ BCMA_CORE_PCIE2, "PCIe Gen2" },
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{ BCMA_CORE_ARM_CR4, "ARM CR4" },
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+ { BCMA_CORE_GCI, "GCI" },
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+ { BCMA_CORE_CMEM, "CNDS DDR2/3 memory controller" },
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+ { BCMA_CORE_ARM_CA7, "ARM CA7" },
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{ BCMA_CORE_DEFAULT, "Default" },
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};
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@@ -315,6 +318,8 @@ static int bcma_get_next_core(struct bcm
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switch (core->id.id) {
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case BCMA_CORE_4706_MAC_GBIT_COMMON:
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case BCMA_CORE_NS_CHIPCOMMON_B:
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+ case BCMA_CORE_PMU:
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+ case BCMA_CORE_GCI:
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/* Not used yet: case BCMA_CORE_OOB_ROUTER: */
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break;
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default:
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--- a/drivers/net/wireless/b43/main.c
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+++ b/drivers/net/wireless/b43/main.c
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@@ -1215,10 +1215,10 @@ void b43_wireless_core_phy_pll_reset(str
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case B43_BUS_BCMA:
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bcma_cc = &dev->dev->bdev->bus->drv_cc;
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- bcma_cc_write32(bcma_cc, BCMA_CC_CHIPCTL_ADDR, 0);
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- bcma_cc_mask32(bcma_cc, BCMA_CC_CHIPCTL_DATA, ~0x4);
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- bcma_cc_set32(bcma_cc, BCMA_CC_CHIPCTL_DATA, 0x4);
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- bcma_cc_mask32(bcma_cc, BCMA_CC_CHIPCTL_DATA, ~0x4);
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+ bcma_cc_write32(bcma_cc, BCMA_CC_PMU_CHIPCTL_ADDR, 0);
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+ bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4);
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+ bcma_cc_set32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, 0x4);
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+ bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4);
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break;
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#endif
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#ifdef CONFIG_B43_SSB
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--- a/include/linux/bcma/bcma.h
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+++ b/include/linux/bcma/bcma.h
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@@ -151,6 +151,8 @@ struct bcma_host_ops {
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#define BCMA_CORE_PCIE2 0x83C /* PCI Express Gen2 */
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#define BCMA_CORE_USB30_DEV 0x83D
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#define BCMA_CORE_ARM_CR4 0x83E
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+#define BCMA_CORE_GCI 0x840
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+#define BCMA_CORE_CMEM 0x846 /* CNDS DDR2/3 memory controller */
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#define BCMA_CORE_ARM_CA7 0x847
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#define BCMA_CORE_SYS_MEM 0x849
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#define BCMA_CORE_DEFAULT 0xFFF
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@@ -200,6 +202,7 @@ struct bcma_host_ops {
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#define BCMA_PKG_ID_BCM4707 1
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#define BCMA_PKG_ID_BCM4708 2
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#define BCMA_PKG_ID_BCM4709 0
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+#define BCMA_CHIP_ID_BCM47094 53030
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#define BCMA_CHIP_ID_BCM53018 53018
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/* Board types (on PCI usually equals to the subsystem dev id) */
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--- a/include/linux/bcma/bcma_driver_chipcommon.h
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+++ b/include/linux/bcma/bcma_driver_chipcommon.h
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@@ -217,6 +217,11 @@
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#define BCMA_CC_CLKDIV_JTAG_SHIFT 8
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#define BCMA_CC_CLKDIV_UART 0x000000FF
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#define BCMA_CC_CAP_EXT 0x00AC /* Capabilities */
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+#define BCMA_CC_CAP_EXT_SECI_PRESENT 0x00000001
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+#define BCMA_CC_CAP_EXT_GSIO_PRESENT 0x00000002
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+#define BCMA_CC_CAP_EXT_GCI_PRESENT 0x00000004
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+#define BCMA_CC_CAP_EXT_SECI_PUART_PRESENT 0x00000008 /* UART present */
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+#define BCMA_CC_CAP_EXT_AOB_PRESENT 0x00000040
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#define BCMA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */
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#define BCMA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */
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#define BCMA_CC_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */
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@@ -351,12 +356,12 @@
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#define BCMA_CC_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
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#define BCMA_CC_PMU_RES_REQT 0x0644 /* PMU res req timer */
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#define BCMA_CC_PMU_RES_REQM 0x0648 /* PMU res req mask */
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-#define BCMA_CC_CHIPCTL_ADDR 0x0650
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-#define BCMA_CC_CHIPCTL_DATA 0x0654
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-#define BCMA_CC_REGCTL_ADDR 0x0658
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-#define BCMA_CC_REGCTL_DATA 0x065C
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-#define BCMA_CC_PLLCTL_ADDR 0x0660
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-#define BCMA_CC_PLLCTL_DATA 0x0664
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+#define BCMA_CC_PMU_CHIPCTL_ADDR 0x0650
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+#define BCMA_CC_PMU_CHIPCTL_DATA 0x0654
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+#define BCMA_CC_PMU_REGCTL_ADDR 0x0658
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+#define BCMA_CC_PMU_REGCTL_DATA 0x065C
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+#define BCMA_CC_PMU_PLLCTL_ADDR 0x0660
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+#define BCMA_CC_PMU_PLLCTL_DATA 0x0664
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#define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
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#define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
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#define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
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@@ -566,17 +571,16 @@
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* Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
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*/
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struct bcma_chipcommon_pmu {
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+ struct bcma_device *core; /* Can be separated core or just ChipCommon one */
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u8 rev; /* PMU revision */
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u32 crystalfreq; /* The active crystal frequency (in kHz) */
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};
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-#ifdef CONFIG_BCMA_DRIVER_MIPS
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+#ifdef CONFIG_BCMA_PFLASH
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struct bcma_pflash {
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bool present;
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- u8 buswidth;
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- u32 window;
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- u32 window_size;
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};
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+#endif
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#ifdef CONFIG_BCMA_SFLASH
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struct bcma_sflash {
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@@ -602,6 +606,7 @@ struct bcma_nflash {
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};
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#endif
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+#ifdef CONFIG_BCMA_DRIVER_MIPS
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struct bcma_serial_port {
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void *regs;
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unsigned long clockspeed;
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@@ -621,8 +626,9 @@ struct bcma_drv_cc {
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/* Fast Powerup Delay constant */
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u16 fast_pwrup_delay;
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struct bcma_chipcommon_pmu pmu;
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-#ifdef CONFIG_BCMA_DRIVER_MIPS
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+#ifdef CONFIG_BCMA_PFLASH
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struct bcma_pflash pflash;
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+#endif
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#ifdef CONFIG_BCMA_SFLASH
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struct bcma_sflash sflash;
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#endif
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@@ -630,6 +636,7 @@ struct bcma_drv_cc {
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struct bcma_nflash nflash;
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#endif
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+#ifdef CONFIG_BCMA_DRIVER_MIPS
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int nr_serial_ports;
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struct bcma_serial_port serial_ports[4];
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#endif /* CONFIG_BCMA_DRIVER_MIPS */
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@@ -663,6 +670,19 @@ struct bcma_drv_cc_b {
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#define bcma_cc_maskset32(cc, offset, mask, set) \
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bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
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+/* PMU registers access */
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+#define bcma_pmu_read32(cc, offset) \
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+ bcma_read32((cc)->pmu.core, offset)
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+#define bcma_pmu_write32(cc, offset, val) \
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+ bcma_write32((cc)->pmu.core, offset, val)
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+
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+#define bcma_pmu_mask32(cc, offset, mask) \
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+ bcma_pmu_write32(cc, offset, bcma_pmu_read32(cc, offset) & (mask))
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+#define bcma_pmu_set32(cc, offset, set) \
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+ bcma_pmu_write32(cc, offset, bcma_pmu_read32(cc, offset) | (set))
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+#define bcma_pmu_maskset32(cc, offset, mask, set) \
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+ bcma_pmu_write32(cc, offset, (bcma_pmu_read32(cc, offset) & (mask)) | (set))
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+
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extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
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extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
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--- a/drivers/bcma/bcma_private.h
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+++ b/drivers/bcma/bcma_private.h
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@@ -44,10 +44,6 @@ int bcma_sprom_get(struct bcma_bus *bus)
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void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
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void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
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void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
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-#ifdef CONFIG_BCMA_DRIVER_MIPS
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-void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
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-extern struct platform_device bcma_pflash_dev;
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-#endif /* CONFIG_BCMA_DRIVER_MIPS */
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/* driver_chipcommon_b.c */
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int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb);
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@@ -59,6 +55,21 @@ void bcma_pmu_init(struct bcma_drv_cc *c
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u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
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u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
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+/**************************************************
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+ * driver_chipcommon_sflash.c
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+ **************************************************/
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+
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+#ifdef CONFIG_BCMA_PFLASH
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+extern struct platform_device bcma_pflash_dev;
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+int bcma_pflash_init(struct bcma_drv_cc *cc);
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+#else
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+static inline int bcma_pflash_init(struct bcma_drv_cc *cc)
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+{
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+ bcma_err(cc->core->bus, "Parallel flash not supported\n");
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+ return 0;
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+}
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+#endif /* CONFIG_BCMA_PFLASH */
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+
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#ifdef CONFIG_BCMA_SFLASH
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/* driver_chipcommon_sflash.c */
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int bcma_sflash_init(struct bcma_drv_cc *cc);
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--- a/drivers/bcma/driver_gpio.c
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+++ b/drivers/bcma/driver_gpio.c
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@@ -229,6 +229,7 @@ int bcma_gpio_init(struct bcma_drv_cc *c
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case BCMA_CHIP_ID_BCM4707:
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case BCMA_CHIP_ID_BCM5357:
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case BCMA_CHIP_ID_BCM53572:
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+ case BCMA_CHIP_ID_BCM47094:
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chip->ngpio = 32;
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break;
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default:
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--- a/drivers/bcma/driver_mips.c
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+++ b/drivers/bcma/driver_mips.c
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@@ -14,8 +14,6 @@
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#include <linux/bcma/bcma.h>
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-#include <linux/mtd/physmap.h>
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-#include <linux/platform_device.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <linux/serial_reg.h>
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@@ -32,26 +30,6 @@ enum bcma_boot_dev {
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BCMA_BOOT_DEV_NAND,
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};
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-static const char * const part_probes[] = { "bcm47xxpart", NULL };
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-
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-static struct physmap_flash_data bcma_pflash_data = {
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- .part_probe_types = part_probes,
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-};
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-
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-static struct resource bcma_pflash_resource = {
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- .name = "bcma_pflash",
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- .flags = IORESOURCE_MEM,
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-};
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-
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-struct platform_device bcma_pflash_dev = {
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- .name = "physmap-flash",
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- .dev = {
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- .platform_data = &bcma_pflash_data,
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- },
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- .resource = &bcma_pflash_resource,
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- .num_resources = 1,
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-};
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-
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/* The 47162a0 hangs when reading MIPS DMP registers registers */
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static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
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{
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@@ -272,48 +250,11 @@ static enum bcma_boot_dev bcma_boot_dev(
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return BCMA_BOOT_DEV_SERIAL;
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}
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-static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
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+static void bcma_core_mips_nvram_init(struct bcma_drv_mips *mcore)
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{
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struct bcma_bus *bus = mcore->core->bus;
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- struct bcma_drv_cc *cc = &bus->drv_cc;
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- struct bcma_pflash *pflash = &cc->pflash;
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enum bcma_boot_dev boot_dev;
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- switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
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- case BCMA_CC_FLASHT_STSER:
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- case BCMA_CC_FLASHT_ATSER:
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- bcma_debug(bus, "Found serial flash\n");
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- bcma_sflash_init(cc);
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- break;
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- case BCMA_CC_FLASHT_PARA:
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- bcma_debug(bus, "Found parallel flash\n");
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- pflash->present = true;
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- pflash->window = BCMA_SOC_FLASH2;
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- pflash->window_size = BCMA_SOC_FLASH2_SZ;
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-
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- if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
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- BCMA_CC_FLASH_CFG_DS) == 0)
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- pflash->buswidth = 1;
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- else
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- pflash->buswidth = 2;
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-
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- bcma_pflash_data.width = pflash->buswidth;
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- bcma_pflash_resource.start = pflash->window;
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- bcma_pflash_resource.end = pflash->window + pflash->window_size;
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-
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- break;
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- default:
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- bcma_err(bus, "Flash type not supported\n");
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- }
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-
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- if (cc->core->id.rev == 38 ||
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- bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
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- if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
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- bcma_debug(bus, "Found NAND flash\n");
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- bcma_nflash_init(cc);
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- }
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- }
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-
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/* Determine flash type this SoC boots from */
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boot_dev = bcma_boot_dev(bus);
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switch (boot_dev) {
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@@ -337,13 +278,10 @@ static void bcma_core_mips_flash_detect(
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void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
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{
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- struct bcma_bus *bus = mcore->core->bus;
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-
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if (mcore->early_setup_done)
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return;
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- bcma_chipco_serial_init(&bus->drv_cc);
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- bcma_core_mips_flash_detect(mcore);
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+ bcma_core_mips_nvram_init(mcore);
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mcore->early_setup_done = true;
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}
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--- a/drivers/bcma/host_pci.c
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+++ b/drivers/bcma/host_pci.c
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@@ -294,7 +294,7 @@ static const struct pci_device_id bcma_p
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4360) },
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- { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
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+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, 0x4365, PCI_VENDOR_ID_DELL, 0x0016) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a0) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) },
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--- a/drivers/bcma/Kconfig
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+++ b/drivers/bcma/Kconfig
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@@ -70,6 +70,11 @@ config BCMA_DRIVER_MIPS
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If unsure, say N
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+config BCMA_PFLASH
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+ bool
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+ depends on BCMA_DRIVER_MIPS
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+ default y
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+
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config BCMA_SFLASH
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bool
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depends on BCMA_DRIVER_MIPS
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--- a/drivers/bcma/Makefile
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+++ b/drivers/bcma/Makefile
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@@ -1,6 +1,7 @@
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bcma-y += main.o scan.o core.o sprom.o
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bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
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bcma-y += driver_chipcommon_b.o
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+bcma-$(CONFIG_BCMA_PFLASH) += driver_chipcommon_pflash.o
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bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
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bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
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bcma-$(CONFIG_BCMA_DRIVER_PCI) += driver_pci.o
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--- /dev/null
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+++ b/drivers/bcma/driver_chipcommon_pflash.c
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@@ -0,0 +1,49 @@
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+/*
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+ * Broadcom specific AMBA
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+ * ChipCommon parallel flash
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+ *
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+ * Licensed under the GNU/GPL. See COPYING for details.
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+ */
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+
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+#include "bcma_private.h"
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+
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+#include <linux/bcma/bcma.h>
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+#include <linux/mtd/physmap.h>
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+#include <linux/platform_device.h>
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+
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+static const char * const part_probes[] = { "bcm47xxpart", NULL };
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+
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+static struct physmap_flash_data bcma_pflash_data = {
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+ .part_probe_types = part_probes,
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+};
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+
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+static struct resource bcma_pflash_resource = {
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+ .name = "bcma_pflash",
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+ .flags = IORESOURCE_MEM,
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+};
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+
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+struct platform_device bcma_pflash_dev = {
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+ .name = "physmap-flash",
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+ .dev = {
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+ .platform_data = &bcma_pflash_data,
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+ },
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+ .resource = &bcma_pflash_resource,
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+ .num_resources = 1,
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+};
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+
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+int bcma_pflash_init(struct bcma_drv_cc *cc)
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+{
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+ struct bcma_pflash *pflash = &cc->pflash;
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+
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+ pflash->present = true;
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+
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+ if (!(bcma_read32(cc->core, BCMA_CC_FLASH_CFG) & BCMA_CC_FLASH_CFG_DS))
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+ bcma_pflash_data.width = 1;
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+ else
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+ bcma_pflash_data.width = 2;
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+
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+ bcma_pflash_resource.start = BCMA_SOC_FLASH2;
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+ bcma_pflash_resource.end = BCMA_SOC_FLASH2 + BCMA_SOC_FLASH2_SZ;
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+
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+ return 0;
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+}
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--- a/drivers/bcma/main.c
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+++ b/drivers/bcma/main.c
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@@ -325,7 +325,7 @@ static int bcma_register_devices(struct
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bcma_register_core(bus, core);
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}
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-#ifdef CONFIG_BCMA_DRIVER_MIPS
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+#ifdef CONFIG_BCMA_PFLASH
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if (bus->drv_cc.pflash.present) {
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err = platform_device_register(&bcma_pflash_dev);
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if (err)
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