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git://git.openwrt.org/openwrt/openwrt.git
synced 2025-11-03 14:34:27 -05:00
b33c185876
This adds clock drivers for the MediaTek MT7988 SoC Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
25 lines
804 B
Diff
25 lines
804 B
Diff
--- a/drivers/clk/mediatek/clk-mtk.h
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+++ b/drivers/clk/mediatek/clk-mtk.h
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@@ -233,6 +233,7 @@ struct mtk_pll_data {
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u32 pcw_reg;
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int pcw_shift;
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u32 pcw_chg_reg;
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+ int pcw_chg_shift;
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const struct mtk_pll_div_table *div_table;
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const char *parent_name;
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u32 en_reg;
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--- a/drivers/clk/mediatek/clk-pll.c
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+++ b/drivers/clk/mediatek/clk-pll.c
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@@ -137,7 +137,10 @@ static void mtk_pll_set_rate_regs(struct
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pll->data->pcw_shift);
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val |= pcw << pll->data->pcw_shift;
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writel(val, pll->pcw_addr);
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- chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
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+ if (pll->data->pcw_chg_shift)
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+ chg = readl(pll->pcw_chg_addr) | BIT(pll->data->pcw_chg_shift);
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+ else
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+ chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
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writel(chg, pll->pcw_chg_addr);
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if (pll->tuner_addr)
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writel(val + 1, pll->tuner_addr);
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