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8b9bd686e7
Fix two hardware initialization issues in the EN7581 PCIe controller and add support for x2 (2-lane) link mode. Fixes: The upstream EN7581 PCIe initialization writes EQ presets and PIPE configuration registers before clk_bulk_prepare_enable(). Since the MAC clocks are not yet running at that point, these register writes are silently dropped, leaving the hardware with default values. This can cause link training failures or suboptimal equalization. Additionally, after link training the MAC may only advertise Gen1-Gen2 capability in the Link Capabilities 2 register despite the PHY being configured for Gen3. A serdes reset toggle forces the MAC to re-read PHY capability, recovering Gen3 8GT/s link speed. Both issues are addressed by separating PERST from the clock callbacks (patch 911), allowing the PCIe controller driver to properly sequence PERST, clock enable, and register writes (patch 912). New feature: PCIe x2 mode support for EN7581 using the NP_SCU system controller for serdes mux routing, PERST management, and lane configuration. Both bonded MACs are configured for x2 operation with proper EQ presets before link training begins. Signed-off-by: Ryan Chen <rchen14b@gmail.com> Link: https://github.com/openwrt/openwrt/pull/21978 Signed-off-by: Robert Marko <robimarko@gmail.com>