Drop upstreamed patches:
* 130-arm64-dts-broadcom-bcmbca-bcm4908-set-brcm-wp-not-co.patch
All other patches automatically refreshed.
Signed-off-by: Stefan Kalscheuer <stefan@stklcode.de>
Link: https://github.com/openwrt/openwrt/pull/20169
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
This is an automatically generated commit.
When doing `git bisect`, consider `git bisect --skip`.
Signed-off-by: Stefan Kalscheuer <stefan@stklcode.de>
Link: https://github.com/openwrt/openwrt/pull/20169
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
This is an automatically generated commit.
When doing `git bisect`, consider `git bisect --skip`.
Signed-off-by: Kyle Hendry <kylehendrydev@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19708
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
After investigating the EAP235-Wall u-boot GPL code, it was found that
the u-boot of this device directly loads the kernel from the SPI NOR
Flash direct access address. However, due to hardware limitation, MT7621
can only remap the first 4MiB Flash. Excluding some partitions before
the kernel, this device can only boot kernels smaller than 0x360000.
This means that unless you install a modified bootloader, the mainline
OpenWrt will no longer work on this model.
Closes: https://github.com/openwrt/openwrt/issues/20500
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/20509
Signed-off-by: Robert Marko <robimarko@gmail.com>
EDUP EP-RT2960S has the similar hardware design as the SIMAX1800T.
The main difference is the arrangement of the GPIO pins
and the location of the MAC address.
Specification
-------------
- SoC : Mediatek MT7621
- RAM : 256 MiB DDR3
- Flash : 128 MiB NAND Flash
- WLAN : Mediatek MT7905 DBDC
- 2.4 GHz : 2x2 MIMO WiFi6
- 5 GHz : 2x2 MIMO WiFi6
- Ethernet : MT7621 built-in 10/100/1000 Mbps 1x WAN; 3x LAN
- UART : 3.3V, 115200n8
- Buttons : 1x RESET; 1x WPS/MESH
- LEDs : 1x Multi-Color(Blue;Green;Red)
- Power : DC 12V1A
- CMIIT ID : 2022AP7163
- TFTP IP :
- server : 192.168.1.254
- router : 192.168.1.28
TFTP Installation(recommend)
------------
1. Set local tftp server IP "192.168.1.254" and NetMask "255.255.255.0".
2. Rename initramfs-kernel.bin to "factory.bin" and put it in the root
directory of the tftp server. tftpd64 is a good choice for Windows.
3. Remove all Ethernet cables and WiFi connections from the PC, except
for the one connected to the EDUP EP-RT2960S. Start the TFTP server, plug
in the power adapter and wait for the OpenWrt system to boot.
4. Backup "firmware" partition and rename it to "firmware.bin". We need
it to back to the stock firmware.
5. Use "fw_printenv" command to list envs. If "firmware_select=2" is
observed then set u-boot env variable via command:
`fw_setenv firmware_select 1`
6. Apply sysupgrade.bin in OpenWrt LuCI.
Web UI Installation
------------
1. Apply update by uploading initramfs-factory.bin to the web UI.
2. Use "fw_printenv" command to list envs. If "firmware_select=2" is
observed then set u-boot env variable via command:
`fw_setenv firmware_select 1`
3. Apply squashfs-sysupgrade.bin in OpenWrt LuCI.
Return to Stock Firmware
----------------------------
Restore the backup firmware partition in the installation step 4.
MAC addresses
-------------
+---------+-------------------+
| | MAC example |
+---------+-------------------+
| LABEL | 24:D5:1C:xx:xx:xx |
| LAN | 24:D5:1C:xx:xx:xx |
| WAN | 24:D5:1C:xx:xx:xx |
| WLAN2G | 24:D5:1C:xx:xx:xx |
| WLAN5G | 26:D5:1C:xx:xx:xx |
+---------+-------------------+
Tips:
-----------
User can use `TFTP Installation` method to recover a brick device.
Signed-off-by: Andrii Kuiukoff <andros.ua@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20600
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The functions iterating through the port statistic/counter (for
initialization or polling) use the generic name "i" for the iterator. This
makes reading the actual body of the loop cumbersome because it is not
clear that various parameters of functions are about a ports.
Suggested-by: Felix Baumann <felix.bau@gmx.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20631
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Some SoC families require table access to get the HW counters. A mutex is
required for this access - which will potentially cause a sleep in the
current context. This is not always possible with .get_stats64 because it
is also called in atomic contexts.
For these SoCs, the retrieval of the current counters in .get_stats64 is
skipped and the counters are simply retrieved a lot more often from the HW.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20631
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
If an architecture doesn't need to sleep for retrieving the current
statistics from the HW, it is possible to directly retrieve the last values
from the HW when .get_stats64 is called. This avoids the stale counters
with the current refresh interval of 60 seconds.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20631
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
On many architectures, retrieving the HW counters from the switch is not
potentially sleeping. This would potentially allow these architectures to
retrieve the most recent values from the HW when .get_stats64 is called.
But because of the global mutex (which may sleep on lock), this would no
longer be possible.
Reintroduce the per port counters lock which protects from parallel
writes+reads of the non-link_stat counters. The locking is made abstract by
using helpers which identify the correct locking mechanism based on the
used read methods of the SoC.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20631
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add MIB data structures and table access routines for the RTL931X family.
These counters can now be exposed through the ethtool statistics interface.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Co-developed-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20631
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Some Realtek SoCs such as the RTL931X store MIB counters in tables rather
than registers. Unlike register reads, table access requires programming
the table control register, setting the command field to determine read or
write, and then polling for completion. This makes it necessary to
implement a separate path for table-based statistics.
Like register-based MIBs, the table-based MIBs also come in two types: STD
and PRIV which will require slightly different implementations.
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20631
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Some Realtek SoCs do not expose MIB counters as simple registers. Instead,
retrieving counters may require blocking operations or take longer than a
normal register read. This makes the existing approach of direct reads
unsuitable. The existing approach uses spin locks which forbid sleeping
inside their context. But some hardware accesses methods (for example table
reads) might block (sleep).
To handle this, the MIB read path is redesigned with two levels of
locking:
* A global mutex protects updates of MIB data from the hardware. This is
necessary because reads can occur both in the polling workqueue and from
ethtool callbacks, also two user threads might call the ethtools
callbacks. A global mutex helps to avoid parallel reads of the same
hardware data. For table reads, this is not necessarily required because
they are already using a table lock. But they are the reason why
spin-locks can no longer be used (see above).
* A per-port spinlock protects the shared memory region where per-port
counters are copied. Avoids reading of half copied values in
.get_stats64()
As part of this change, MIB reads were removed from .get_stats64() since
that callback can be started from an atomic context and must never sleep
(block) in this context. A shared memory region is provided which will be
updated periodically by MIB workqueue and .get_stats64() will simply return
data from the shared memory.
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20631
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This PR fixes support for Cudy r700.
Original PR: https://github.com/openwrt/openwrt/pull/18532
Fixed:
- WAN port functionality;
- RESET button;
- Status LED;
- LAN port names consistent with the chassis;
- Merged partitions "debug", "backup" & "firmware" to one partition "firmware" ("debug" & "backup" contained unimportant data);
- Removed redundant DTS elements.
Installation:
To install OpenWRT, you need the intermediate firmware from Cudy. (U-boot is locked). After installing the intermediate firmware, you can install OpenWRT via sysupgrade.
Recovery:
TFTP available.
1. Place the recovery.bin in the serving directory of your TFTP server.
2. Set your IP to 192.168.1.88/24.
3. Press the “Reset” button of Cudy router and hold it. Before the Cudy router is powered on and before TFTP start to download the firmware, don't release the “Reset” button.
4. Power on the Cudy router.
5. You can release the reset button only when TFTP starts downloading firmware.
6. When the SYSTEM LED turns solid green, the upgrade is complete.
Fixes: 75403dd1d0 ("ramips: add support for Cudy R700")
Signed-off-by: Marcin Leksmark <lexmark3200@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/20756
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Hardware
--------
RockChip RK3528 ARM64 (4 cores)
1/2/4GB LPDDR4 RAM
1x LED (state)
1x Reset button
0/8/16/32/64GB eMMC on-board
Micro-SD Slot
PCIe FPC connector
3x USB 2.0 Port
HDMI/AV OUT
USB Type-C 5V Power
ROCK 2A:
+ 3.5mm audio out
+ 1000 Base-T
+ SYS LED
+ USB 3.0 Port (conflicts with PCIe)
Installation
------------
Uncompress the OpenWrt sysupgrade and write it to a micro SD card or
internal eMMC using dd.
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/20375
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Unset KERNEL_LOADADDR in default profile to avoid using the value
from other boards (if someone forgets to set KERNEL_LOADADDR).
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/20375
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport pending nvmem/thermal/usb updates for rk3528.
These patches are not merged by upstream yet but worthy to have here.
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/20375
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The probe order for PCIe buses and devices is non-deterministic,
making the names eth2 and eth3 unpredictable (they may be swapped).
This patch fixes the names by referencing the device path using
`ucidef_set_network_device_path`.
This patch ensures that the OpenWrt interface name matches the case label.
Fixes: 8ca4caacd0 ("rockchip: Add support for RK3568 LinkEase EasePi R1")
Signed-off-by: Liangbin Lian <jjm2473@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20779
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The MSTI range is 0..4095 but the HW range is only supporting a lower
range - for example 0..63 for RTL930x. But the HW doesn't really need to
know the actual MSTI. It is therefore possible to use a mapping from MSTI
to HW slot to allow a larger range of MSTIs.
Since the CIST (MSTI 0) is always needed, the mapping data structure is
skipping this entry and is always keeping the HW slot 0 for CIST.
This doesn't increase the total number of MSTIs a HW supports.
Suggested-by: Jonas Gorski <jonas.gorski@gmail.com>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The MSTP support (usually implemented by mstpd) requires from the kernel
that a VLAN can associated with an MSTI. At the moment, all these VLANs
just get the msti 0 harcoded on creation. But the
vlan_tables_read()+vlan_tables_write() helper already allow the
modification of the MSTI and only require a minimal hook to expose this
functionality.
It is also necessary to adjust the (M)STP states per MSTI and not only per
port (or for the CIST). The rtl83xx_port_stp_state_set() function was in
theory already capable to modify other MSTIs than CIST - if the msti would
not have been hardcoded to 0.
The userspace can trigger these modifications using netlink:
* (Re)associating VLANs with an MSTI:
bridge vlan global set dev <BR> vid <X> msti <Y>
* Setting the port state in a given MSTI:
bridge mst set dev <PORT> msti <Y> state <Z>
Signed-off-by: Issam Hamdi <ih@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The VLANs and their MSTIs are shared on the realtek switch HW between
bridged and unbridged ports. But the MSTI state cannot be updated for an
unbridged port via DSA. To ensure that the port is still configured
correctly after leaving a bridge, the CIST state updates via DSA must also
be propagated to the MSTI states.
Suggested-by: Jonas Gorski <jonas.gorski@gmail.com>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
When joining a bridge or leaving a bridge, the CIST state will
automatically be adjusted by DSA using .port_stp_state_set(). But MSTIs are
completely unhandled.
If a port is joining a bridge, the default state must be disabled. The MSTP
daemon is then responsible for adjusting the state.
If the bridge is left, the forwarding state must be enforced because VLANs
(and with this also the MSTIs assigned to them) are shared between bridged
and non-bridged ports. An unbridged port must therefore not be left in an
blocked/disabled state for a VLAN (MSTI).
Suggested-by: Jonas Gorski <jonas.gorski@gmail.com>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
If a VLAN doesn't have any members anymore, then it is removed and
implicitly returns back from any MSTI to CIST. The DSA layer will not
create any call to .vlan_msti_set and the driver is required to handle this
directly.
Suggested-by: Jonas Gorski <jonas.gorski@gmail.com>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Each SoC supports a different number of MST(I)s. The code must know this
limitation to correctly reject unsupported MSTIs or to allocate a large
enough mapping table.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The DSA port code is trying to flush associated VLANs whenever the MST
state is changed. This functionality is available on a per port+vid based
using the L2_TBL_FLUSH_CTRL which is already used for the .port_fast_age
callbacks.
Signed-off-by: Issam Hamdi <ih@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The realtek DSA switch driver sets up all VLANs using CIST. It is therefore
not necessary to enforce CIST using the ST_CTRL register.
This allows us later to overwrite the MSTI of VLANs. This is necessary to
get MSTP working on RTL93xx.
Signed-off-by: Issam Hamdi <ih@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This pull request is based on
- the discussions in https://forum.openwrt.org/t/adding-openwrt-support-for-linksys-mr6350
- https://github.com/openwrt/openwrt/pull/11405 which added support for similar devices.
Device Specs:
- IPQ4019
- Quad Core CPU
- 256 MB RAM
- 256 MB FLASH
- 4 LAN ports, 1 WAN port
- 2.4GHz (802.11n) and 5GHz (802.11c) wifi
- 3 LEDs (Red, blue, green) which are routed to one indicator at the top of the case
- 2 buttons (Reset, WPS)
Disassembling the device:
- There are 4 screws at the bottom of the device which must be removed
- Two are under the fron rubber feets
- Two are under the labels in the back (corner next to the rear rubber feets)
Serial interface:
- The serial interface is already populated on the device with a 6-pin header
- Pin 1 is next to the heatsink
- Pinout: 1: 3.3V, 2: TX, 3: RX, 4: unknown, 5: GND, 6: GND
- Settings: 115200, 8N1
Migrating to OpenWrt requires multiple steps:
- Load and boot the initramfs image
- Adapt U-Boot settings to support bigger kernels
- Flash the sysupgrade image
Load and boot initramfs:
- Connect serial interface
- Set up a TFTP server on IP 192.168.1.254
- Copy openwrt-ipq40xx-generic-linksys_mr6350-initramfs-zImage.itb to TFTP server
- Rename file to C0A80101.img
- Boot up the device and stop in U-Boot
- Run the following U-Boot commands after a link has been established:
tftp
bootm
- Initramfs image is started now.
Adapt U-Boot settings to support bigger kernels:
- Run "fw_printenv" in the initramfs image after booting
- There should be an entry kernsize=300000 which indicates the maximum size for the kernel is 3MB
- Execute "fw_setenv kernsize 500000" to increase the max kernel size to 5MB
- Check that the change are applied with "fw_printenv"
Flash the sysupgrade image:
- Default sysupgrade routine either with a initramfs image containing LuCI or via command line.
Revert back to OEM firmware:
- Only tested with FW_MR6350_1.1.3.210129_prod.img
- Flash the OEM firmware via sysupgrade
- Forced update is required
Signed-off-by: Roland Reinl <reinlroland+github@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17977
Signed-off-by: Robert Marko <robimarko@gmail.com>
This device has only half the flash and ram of the RBR20. It also has
two lan ports instead of wan and lan.
Hardware
--------
SOC: Qualcomm IPQ4019
FLASH: 128MB (Winbond W29N01HVSINF)
RAM: 256MB (Winbond W632GU6MB-12)
WIFI: Qualcomm IPQ4019
Qualcomm Atheros QCA9886
ETH: 2x LAN
LED: 5 (4 RGB at top, 1 RG at back)
BTN: WPS, Reset
UART: 115200 8N1 (dotted Pin = VCC) VCC-TX-RX-GND
MAC addresses
-------------
LAN Label MAC (stored in boarddata1 offset 0x0)
2.4G LAN
5GLow LAN + 3 (stored in boarddata1 offset 0xc)
5GUpper LAN + 2 (stored in boarddata1 offset 0x12)
Installation
------------
Either use the vendor ui upgrade method or nmrpflash to install the
factory image.
Signed-off-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20560
Signed-off-by: Robert Marko <robimarko@gmail.com>
This device shares a lot of similarities with the LBR20 - the RBR20 just
misses the LTE modem and its formfactor is alot smaller. Other than that
the LED configuration matches other RBR devices but the RBR20 has less
LEDs than its larger counterparts.
Hardware
--------
SOC: Qualcomm IPQ4019
FLASH: 256MB (Winbond W29N02GVSIAF)
RAM: 512MB (Nanya NT5CC256M16EP-EK)
WIFI: Qualcomm IPQ4019
Qualcomm Atheros QCA9886
ETH: 1x WAN, 1x LAN
LED: 5 (4 RGB at top, 1 RG at back)
BTN: WPS, Reset
UART: 115200 8N1 (dotted Pin = VCC) VCC-TX-RX-GND
MAC addresses
-------------
LAN Label MAC (stored in boarddata1 offset 0x0)
WAN LAN + 1 (stored in boarddata1 offset 0x6)
2.4G LAN
5GLow LAN + 3 (stored in boarddata1 offset 0xc)
5GUpper LAN + 2 (stored in boarddata1 offset 0x12)
Installation
------------
Either use the vendor ui upgrade method or nmrpflash to install the
factory image.
Signed-off-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20560
Signed-off-by: Robert Marko <robimarko@gmail.com>
RTL838x+RTL839x both configure a default QoS behavior with a default
mapping. This also needs to be added to RTL93xx to ensure a consistent
behavior:
* Set the default mapping between DSCP and priority: prio = dscp >> 3.
* Set the default mapping between internal priority and queues
* Set uniform prioritization of queues (as with other SoCs)
Signed-off-by: Issam Hamdi <ih@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20640
Signed-off-by: Robert Marko <robimarko@gmail.com>
If link aggregation with LACP is activated, we must send out the LACP
packets on the physical port and not on a logic port. Otherwise, the per
port packets might be (rebalanced) between the different ports in a link
aggregation group.
Such rebalancing breaks 802.3ad and will leave ports in a churned state.
Fixes: 8c42e63a69 ("realtek: rtl93xx: fix incorrect destination port selection")
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20728
Signed-off-by: Robert Marko <robimarko@gmail.com>
If ports of a RTL93xx switch are not added to a port matrix then they are
not used for the link aggregation. As result, communication will then just
break on non-primary interfaces.
This can be reproduced in balanced-xor and 802.3ad bandwidth mode.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20729
Signed-off-by: Robert Marko <robimarko@gmail.com>
Commit 56e9a73d0b added support for configuring the SerDes polarity for
both RTL930X and RTL931X. Based on the code in the Realtek SDK in [1]
and [2], in both cases the same register bits are set. Thus, a common
implementation was provided which worked with e.g. USXGMII or 10GBase-R
configured SerDes.
However, after further tests, a strange issue occured where it didn't
work that well for all SerDes configurations. While running fine for
10GBase-R links on two adjacent SerDes, it didn't for 1000Base-X links
on one of two adjacent SerDes with the link not being detected as a
symptom.
Diving into the SDK again revealed that the referenced implementation of
polarity configuration is (by accident or by purpose) misleading. While
[1] and [3] for RTL930X match, [2] and [4] for RTL931X actually don't.
[4] writes the bits for the 1G polarity setting on different background
SerDes, thus in another frontend page.
Split implementations for RTL930X and RTL931X again and adjust the one
for RTL931X according to [4]. This resolves the issues with 1000Base-X
behavior.
[1] 69d2890a2e/sources/rtk-xgs1210/src/hal/phy/phy_rtl9300.c (L1384)
[2] 69d2890a2e/sources/rtk-xgs1210/src/hal/phy/phy_rtl9310.c (L3479)
[3] 69d2890a2e/sources/rtk-xgs1210/src/dal/longan/dal_longan_construct.c (L2246)
[4] 69d2890a2e/sources/rtk-xgs1210/src/dal/mango/dal_mango_construct.c (L1550)
Fixes: 56e9a73d0b ("realtek: pcs: rtl93xx: provide proper SerDes polarity
configuration")
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20767
Signed-off-by: Robert Marko <robimarko@gmail.com>
The MikroTik RouterBOARD 962UiGS-5HacT2HnT (hAP ac) currently comes up
with random MAC addresses. Assign the MAC addresses from hard_config for
LAN and WAN ports.
Fixes: c2140e32ce ("ath79: add support for MikroTik RouterBOARD 962UiGS-5HacT2HnT (hAP ac)")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Link: https://github.com/openwrt/openwrt/pull/20782
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add mt7987-2p5g-phy-firmware to DEVICES_PACKAGES of the MT7987A RFB as
well as the BananaPi R4 Lite.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Use skb->encapsulation flag instead of skb_tnl_header_len() to detect
encapsulated packets. Prevents false positives on non-encapsulated packets.
Reported-by: Mason-cw Chang (張哲維) <Mason-cw.Chang@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Usage of strlcpy results in a compilation error. strscpy is preferred
anyways and equivalent for our case.
Signed-off-by: David Bauer <mail@david-bauer.net>
This is an automatically generated commit which aids following Kernel patch
history, as git will see the move and copy as a rename thus defeating the
purpose.
For the original discussion see:
https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
This is an automatically generated commit.
When doing `git bisect`, consider `git bisect --skip`.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
CMCC PZ-L8 is a 2.4/5 GHz band 11ax (Wi-Fi 6) router, based on IPQ5000.
Specifications:
- SoC : Qualcomm IPQ5000
- RAM : Integrated 256MiB DDR3L
- Flash : 128 MiB SPI-NAND (ESMT F50D1G41LB)
- WLAN : 2.4/5 GHz 2T2R
- 2.4 GHz : Qualcomm IPQ5000 (SoC)
- 5 GHz : Qualcomm Atheros QCN6102
- Ethernet : 4x 10/100/1000 Mbps
- switch : Qualcomm Atheros QCA8337
- LEDs/Keys (GPIO) : 2x LEDs, 2x Keys
- UART : Through-hole on PCB, 4pins in the middle of the black aluminum heat sink
- assignment : 3.3V, GND,TX, RX (from left to right)
- settings : 115200n8
- Power : 12 VDC, 1 A
Flashing Instructions:
1. SSH Method
(1) Enable SSH on the stock firmware
a. Version 501.8 and 501.9:
Log in to http://192.168.10.1 with the password on the sticker
Append "/admin/system/admin" to the URL and press Enter
Delete "Dropbear instance", click "Add instance", then "Save and Apply"
Reboot the router
b. Version 501.11 and 501.12:
While the router is running the stock firmware, press and hold the reset button for 20-30 seconds
Open http://192.168.10.1:56781 and login with username "root" and the password on the sticker
Run "vi /etc/config/dropbear" and delete the line "option enable '0'"
Reboot the router
(2) Upload the factory.ubi file to router's /tmp directory (using scp or wget)
and execute the following commands in the router's shell
export rootfs=$(cat /proc/mtd | grep rootfs | grep -v _ | cut -d: -f1)
ubidetach -f -p /dev/${rootfs}
ubiformat /dev/${rootfs} -y -f /tmp/factory.ubi
2. U-Boot Method using UBI Image
Place the factory.ubi file on your TFTP server, enter U-Boot CLI and exec these commands
tftpboot <your_tftp_server_ip>:factory.ubi
flash rootfs
reset
3. U-Boot Method using initramfs Image
(1) Place the openwrt-*-initramfs-fit-uImage.itb file on your TFTP server
and rename it to initramfs.bin
(2) Enable serial console, enter to U-Boot CLI and exec these commands
tftpboot <your_tftp_server_ip>:initramfs.bin
bootm
(3) Once boot completed, upload the sysupgrade.bin file to router's /tmp directory
(using scp or wget) and execute the following command in openwrt shell
sysupgrade -n /tmp/sysupgrade.bin
Switching to the Stock Firmware:
Please follow the commit 3b7d72bc2e
Partition Layout (Stock Firmware):
0x000000000000-0x000000080000 : "0:SBL1"
0x000000080000-0x000000100000 : "0:MIBIB"
0x000000100000-0x000000140000 : "0:BOOTCONFIG"
0x000000140000-0x000000180000 : "0:BOOTCONFIG1"
0x000000180000-0x000000280000 : "0:QSEE"
0x000000280000-0x000000380000 : "0:QSEE_1"
0x000000380000-0x0000003c0000 : "0:DEVCFG"
0x0000003c0000-0x000000400000 : "0:DEVCFG_1"
0x000000400000-0x000000440000 : "0:CDT"
0x000000440000-0x000000480000 : "0:CDT_1"
0x000000480000-0x000000500000 : "0:APPSBLENV"
0x000000500000-0x000000640000 : "0:APPSBL"
0x000000640000-0x000000780000 : "0:APPSBL_1"
0x000000780000-0x000000880000 : "0:ART"
0x000000880000-0x000000900000 : "0:TRAINING"
0x000000900000-0x000004300000 : "rootfs"
0x000004300000-0x000007d00000 : "rootfs_1"
Notes:
This device is almost the same as ELECOM WRC-X3000GS2, including partition layout and the dual-boot feature.
Known Issues:
- All Wi-Fi related peripherals are disabled in device tree, since 256 MiB RAM is too few for ath11k.
- This device has another version with nand flash FM25SL01, which is not supported at the moment.
https://github.com/immortalwrt/immortalwrt/blob/master/target/linux/mediatek/patches-6.12/342-mtd-spinand-Support-fmsh.patch
MAC Addresses:
Interface MAC Address Location (binary)
LAN A4:39:B6:xx:xx:9D (0:ART, 0x00-0x05)
WAN A4:39:B6:xx:xx:9E (0:ART, 0x06-0x0B)
2.4 GHz A4:39:B6:xx:xx:9F (0:ART, 0x0C-0x11)
5 GHz A4:39:B6:xx:xx:A0 (0:ART, 0x12-0x17)
Signed-off-by: Chang Liu <jssqliuchang@gmail.com>
`$(MAKE) package_index` will generate Packages.sig if signing is enabled, and Packages.sig is always newer than Packages.gz, cause repeated generation of package index on next build. So we should ignore Packages.sig.
Signed-off-by: Liangbin Lian <jjm2473@gmail.com>
The "old" QCA8084 PHY driver does not implement 10g-qxgmii support.
This is blocking several devices which use the QCA8084 form being
merged. Qualcomm has provided updated drivers for the MAC (ppe), PCS,
and PHY via github. We only need to update the PHY driver.
Update the QCA8084 PHY driver using the patches provided by Qualcomm.
Re-organize the patches so that the changes go into the existing
patches. The SERDES functionality is new, so it gets new patches. This
is sufficient to enable 10g-qxgmii on ipq95xx platforms.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20721
Signed-off-by: Robert Marko <robimarko@gmail.com>
Replace Airoha AN7583 pinctrl patch with upstream version as it has been
accepted upstream. Add the related kernel version tag to identify it.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The unit-address of the ubi partition was @a9c0000 but the partition
actually starts at offset 0x0ad00000. Ideally they should match, so
align them.
Signed-off-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20733
Signed-off-by: Robert Marko <robimarko@gmail.com>
The name "is_lagmember" implies that the port is part of a LAG. But this
information is already stored in lagmembers. In reality, it is stored the
non-primary LAG members. Renaming it accordingly, makes the code a lot more
readable
Also the type (u32 array) looks like it would contain some kind of large id
(like the group ID). But it only stores a single bit. It is more appropriate
to just use a single bit per port.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20707
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The names of the LAG variables in struct rtl838x_switch_priv are not self
explaining. They are even suggesting that they are dealing with information
which are actually stored in a different variable. As first step, document
their meaning.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20707
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
There is no need to check conditions in rtl83xx_lag_add()/rtl83xx_lag_del()
when they are already checked in
rtl83xx_port_lag_join()/rtl83xx_port_lag_leave().
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20707
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
It is not necessary to have a private LAG id allocation when the shared DSA
code already provides the complete infrastructure for it.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20707
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The DSA code is responsible to inform the driver about link aggregation
changes. Having a second one which behaves slightly different makes the
whole process fragile and creates hard to debug problems.
It also complicates the code because the secondary event handler can also
not rely on shared DSA state to handle things like LAG ID.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20707
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The rtl83xx_lag_can_offload() function always returned an error because
ds->num_lag_ids was never set. This basically disabled the DSA lag
configuration completely.
Drop the private n_lag variable and instead use the DSA specific one. This
ensures that all the code always has the same reference for the number of
LAGs.
Fixes: 32e5b5ee6b ("realtek: Add Link Aggregation (aka trunking) support")
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20707
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Commit 8ca4caacd0 ("rockchip: Add support for RK3568 LinkEase EasePi R1")
forgot to include the SoC recipe, which leads KERNEL_LOADADDR undefined.
Fixes: 8ca4caacd0 ("rockchip: Add support for RK3568 LinkEase EasePi R1")
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/20722
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The ifname was renamed to `lan`/`wan` in commit 1f1db75432
("rockchip: make NIC name predictable for Radxa E52C/ROCK 5 ITX/ROCK 5T"),
update accordingly.
Fixes: 1f1db75432 ("rockchip: make NIC name predictable for Radxa E52C/ROCK 5 ITX/ROCK 5T")
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/20722
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Th function to set the mangement frames receive actions is only used in the
SoC specific files. They can therefore be kept local without any
declaration in headers.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20704
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The code for the RTL930x management action configuration was cleaned up
significantly for commit 75fe6b2d0b ("realtek: rtl930x: Add support for
trapping management frames"). Sync these changes to RTL931x to make it
easier to extend both implementations.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20704
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport upstream patch fixing out of order DMA access for ethernet
driver. This is relevant in the context of QoS when packets doesn't
follow linear handling by QDMA HW.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
KConfig flag have an extra whitespace for CONFIG_PHY_AIROHA_USB and
value is not ignored.
Drop the extra whitespace to correctly ignore the value on kernel
compilation.
Fixes: c5b12fc02a ("airoha: Introduce support for Airoha AN7583 SoC")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
As per #19596 - this allows eg, modifying the bootcmd etc.
This has been useful when testing on e.g the -48, where `rtk network on` is required for the SFP ports.
Signed-off-by: Joe Holden <jwh@zorins.us>
Link: https://github.com/openwrt/openwrt/pull/19913
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The ports are physically labelled in reverse order on the device.
This patch aligns logical names with physical ones.
LED order on front of device is correct after this patch.
Fixes: 9d66b8b312
Signed-off-by: Thibaut VARÈNE <hacks@slashdirt.org>
Link: https://github.com/openwrt/openwrt/pull/20528
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
After switching to 6.12, time to remove 6.6 support.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20672
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
No new reggresions was observed. Time to switch to 6.12.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20672
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The probe order for PCIe buses and devices is non-deterministic,
making the names eth0 and eth1 unpredictable (they may be swapped).
This patch fixes the names by referencing the device path using
`ucidef_set_network_device_path`.
The mapping between silkscreen labels on the board/case and OpenWrt
interface names is as follows:
- E52C
LAN: lan
WAN: wan
- ROCK 5 ITX
RJ45 1: eth0
RJ45 2: eth1
- ROCK 5T
RJ45_1: eth0
RJ45_2: eth1
For Radxa E52C, this breaks compatibility of the network config;
therefore, set DEVICE_COMPAT_VERSION to `1.1`.
Fixes: d16d2765bd ("rockchip: add support for Radxa E52C")
Fixes: 0839345211 ("rockchip: add support for Radxa ROCK 5 ITX/ITX+")
Fixes: 4a78af9876 ("rockchip: add support for Radxa ROCK 5T")
Link: https://github.com/openwrt/openwrt/issues/20202
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/20608
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Hardware:
- SoC: MediaTek MT7621DAT
- Flash: 16 MiB XM25QH128C
- RAM: 128 MiB
- WLAN: 2.4 GHz (MT7603E, 11n), 5 GHz (MediaTek MT7613BEN, 11ac)
- Ethernet: 1x10/100/1000 Mbps LAN
- Buttons: 1 Reset button, 1 WPS button
- LEDs: 5x Green
- Serial Console: unpopulated header 115200 8n1 (silkscreen on PCB)
- Power: POE 802.3af (37-57V DC)
MAC addresses:
+---------+-------------------+-----------+
| | MAC | Algorithm |
+---------+-------------------+-----------+
| LAN | 80:af:ca:xx:xx:x0 | label |
| WLAN 2g | 80:af:ca:xx:xx:x0 | label |
| WLAN 5g | 82:af:ca:xx:xx:x1 | +1 |
+---------+-------------------+-----------+
Installation:
The factory firmware is locked: you can only work with Cudy signed firmware.
Download a intermediate firmware signed by Cudy here:
https://www.cudy.com/blogs/faq/openwrt-software-download
After that, login to the router (192.168.10.254, password "admin") and install the intermediate firmware.
If you can reach LuCI or SSH now on the intermediate firmware, just use the sysupgrade image with the 'Keep settings' option turned off.
Special thanks to Daniel de Kock for starting the porting work at #16265.
Signed-off-by: Luis Mita <luis@luismita.com>
Co-Authored-By: Daniel de Kock <daniel@riot.network>
Co-Authored-By: Hauke Mehrtens <hauke@hauke-m.de>
Link: https://github.com/openwrt/openwrt/pull/20268
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Allow to configure SerDes polarity in device tree. To achieve this, add
new device tree properties that can be set in the device tree definition
of the SerDes, are read by the PCS driver during probe and are applied
upon SerDes setup.
This may be required for supporting new devices as the SerDes polarity
is usually subject to the vendors board design and defined in the
hardware profile (HWP) in the SDK. Most importantly, it is quite an
important step towards being able to setup everything on our own instead
of relying on the bootloader.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20648
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The configuration code for RTL930X already provides setting the SerDes
TX and RX PN polarity. This is covered by a function called
'..._sds_mac_link_config'. But despite its name, this function only sets
the SerDes polarity and nothing more.
Moreover, this was called always with 'not inverted' in the SerDes setup
code and thus not really allowing to be configured.
At first, streamline the SerDes polarity configuration code. Rename the
function to reflect what it actually does instead of giving the
impression of doing more. Improve the implementation of this for better
readability.
As the implementation, page, register, bits, etc. are exactly the same
for both RTL930X and RTL931X (compare [1] and [2]), move and name it
accordingly so we can also add support for RTL931X.
[1] 69d2890a2e/sources/rtk-xgs1210/src/hal/phy/phy_rtl9300.c (L1384)
[2] 69d2890a2e/sources/rtk-xgs1210/src/hal/phy/phy_rtl9310.c (L3479)
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20648
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Change return value from -EINVAL to -ENOENT for the TRX parser
workaround patch as it's better suited and it's the common exit error
for parser failing parsing for expected condition (partition not init,
zero partition found in the schema, magic values not matching)
Also this is needed for a pending upstream patch that will permit parser
to fail and be skipped for subpartitions only with the -ENOENT error.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
This commit adds support for TP-LINK BE450.
Device specification
--------------------
SoC Type: MediaTek MT7988D, Cortex-A73, 64-bit
RAM: 512MB
Flash: SPI NAND GigaDevice (128 MiB)
Ethernet: MediaTek MT7531AE (3 Ports) + 2.5GbE (internal MT7988 phy) + 10GbE (RTL8261N)
WLAN: MT7992
WLAN 2g: MediaTek MT7975N, b/g/n/ax/be, MIMO 4x4
WLAN 5g: MediaTek MT7979N, a/n/ac/ax/be, MIMO 4x4
LEDs: 8 LEDs, 1 status blue, 2x WIFI blue, 2x Internet
blue/orange, 1 LAN blue, 1 usb blue, 1 wps blue, gpio-controlled
Button: 2 (Reset, WPS)
USB port: Yes
Power: 12 VDC, 2 A
Connector: Barrel
Bootloader: Main U-Boot - U-Boot 2023.10-rc4. Additionally, ubi0
partition contain "seconduboot" (also U-Boot 2023.10-rc4)
Serial console (UART), unpopulated, located near the power connector
---------------------
heatsink
| |
| |
| | +----+-----+------+-------+ +-----------------+
| | | TX | RX | GND | +3.3V | | power connector |
+---+ +----+-----+------+-------+ +-----------------+
|
Don't connect ----+
Disassemble: rm the 2 screws at the bottom and the one at the backside.
un-clip the case starting at the edge above the LEDs.
Installation (UART)
-------------------
1. Place OpenWrt initramfs image on tftp server with IP 192.168.1.2
2. Attach UART, switch on the router and interrupt the boot process by
pressing 'Ctrl-C'
3. Load and run OpenWrt initramfs image:
tftpboot 0x50000000 openwrt-mediatek-filogic-tplink_be450-initramfs-kernel.bin && bootm 0x50000000
4. Run 'sysupgrade -n' with the sysupgrade OpenWrt image
Note: the 10GbE (RTL8261N) is only working if reverting this Realtek target specific commit:
b77fa45d12
The second ubi partition (ubi1) is empty and there is no known
dual-partition mechanism, neither in u-boot nor in the stock firmware.
NMBM is not used.
Not Working: WED, if activated, MT7992 isn't recognized any more.
Signed-off-by: Dirk Buchwalder <buchwalder@posteo.de>
Link: https://github.com/openwrt/openwrt/pull/20398
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Return 0 if the current mtd is inactive or no valid header/rootfs found,
instead of -ENODEV.
Linux Kernel 6.7 and later versions handle all errors returned by mtd
parsers, including -ENODEV as error. So '0' needs to be returned if no
child partitions were not parsed.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20697
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Also the MT7987 RFB accidentally already set the not-yet-existing
mt798x-2p5g-phy-firmware-internal package as one of the DEVICE_PACKAGES.
This currently breaks the build, so remove it for now. Also remove stray
'blkid' package from DEVICE_PACKAGES which was accidentally copied from
MediaTek's SDK.
Fixes: 9de7189ed4 ("mediatek: build image for MT7987 RFB")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
The Plasma Cloud MCX3 Media Converter is a 3 port multi-GBit switch with
2x 10/100/1000/2500BaseT Ethernet ports and 1x SFP+ module slot.
Hardware:
- RTL9302C SoC
- Macronix MX25L25645G (32MB flash)
- Winbond W632GU6rB-11 (256MB DDR3 SDRAM)
- RTL8224 4x 10m/100m/1/2.5 Gigabit PHY
- IC+ IP802AR POE+ PSE controller
The media converter is powered by 54 Volts 1.2A barrel connector. The
internal TTL serial connector can be used to access the terminal. Pins from
1: TX RX (unused) GND. Serial connection is via 115200 baud, 8N1.
A reset button is accessible through a hole next to the SFP+ module slot.
Installation
------------
* The device can be flashed by using sysupgrade command. Either from the
original vendor firmware or using an initramfs (see "Debug")
* Connect serial as per the layout above. Connection parameters: 115200 8N1
* The image must be copied using scp to /tmp of the device
scp openwrt-realtek-rtl930x-plasmacloud_mcx3-squashfs-sysupgrade.bin root@[IP address of the device]:/tmp/
* start sysupgrade without saving the original vendor configuration
sysupgrade -n /tmp/openwrt-realtek-rtl930x-plasmacloud_mcx3-squashfs-sysupgrade.bin
Installation via u-boot
-----------------------
If you have an TFTP server connected to the switch, it is possible to
directly install the device using the factory image from u-boot
# setup networking and IP of TFP server
rtk network on
setenv ipaddr 10.100.100.99
setenv serverip 10.100.100.20
# get factory image
tftp 0x84000000 factory.bin
# erase firmware partitions
sf probe 0
sf erase 0x100000 0x01f00000
# write firmware to both partitions
sf write ${fileaddr} 0x100000 ${filesize}
sf write ${fileaddr} 0x1080000 ${filesize}
# adjust the boot commands
setenv bootargs "mtdparts=spi0.0:896k(u-boot),64k(u-boot-env),64k(u-boot-env2),15872k(inactive),15872k(firmware2)"
setenv bootcmd "rtk init; bootm 0xb5080000"
# restart
reset
Debug
-----
* Connect serial as per the layout above. Connection parameters: 115200 8N1.
* A tftp server is required, tftpd-hpa works well.
* Power the device, at U-Boot start rapidly hit Esc key to stop autoboot
* Enable network:
rtk network on
* Change ip address of device:
setenv ipaddr 192.168.1.6
* Download initramfs from TFTP server:
tftpboot 0x84000000 192.168.1.111:openwrt-realtek-rtl930x-plasmacloud_mcx3-initramfs-kernel.bin
* Boot loaded file:
bootm 0x84000000
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20625
Signed-off-by: Robert Marko <robimarko@gmail.com>
Because the firmware has not yet been accepted in linux-firmware we
cannot yet package mt7987-2p5g-phy-firmware-internal. Remove it from
DEVICE_PACKAGES of the BPi-R4-mini until the an upcoming linux-firmware
release will come with this firmware included, allowing us to then
create that package.
Fixes: 8b6c6978d6 ("mediatek: add support for BananaPi BPi-R4 Lite")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
The RTL930x and RTL931x have an ingress and egress bandwidth controller for
each port. They can can be used to reduce the throughput for each port.
They can be programmed via the the DSA flower offloading capabilities. Only
a limited functionality (bytes based rate limiter for ingress/egress) is
supported.
With kmod-sched-act-police, kmod-sched-flower and tc installed, each port
can have its ingress/egress rate limit applied in hardware using:
# tc qdisc del dev lan1 clsact
tc qdisc add dev lan1 clsact
tc filter add dev lan1 ingress flower skip_sw action police rate 100mbit burst 64k conform-exceed drop
tc filter add dev lan1 egress flower skip_sw action police rate 150mbit burst 64k conform-exceed drop
Signed-off-by: Issam Hamdi <ih@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20663
Signed-off-by: Robert Marko <robimarko@gmail.com>
On RTL930x, each SerDes pair shares a set of PLLs with different
capabilities (LC PLL: 1G/2.5G/10G, ring PLL: 1G/2.5G). In principle,
this allows any combination of speeds on a SerDes pair. However, it
creates a special case when trying to configure a SerDes for 10G while
the LC PLL is already in use at a slower speed for the neighbor SerDes.
The current implementation just gives up in that case. Instead, free up
the LC PLL by reconfiguring the neighbor SerDes to the ring PLL.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/20568
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit fixes mistaken executable bit on dts files.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/20676
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
It is not necessary to have two different family_id checks directly after
another. It is simpler to just combine both into one.
Suggested-by: Álvaro Fernández Rojas <noltari@gmail.com>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20637
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
The rtl838x_rate_control_init() and rtl839x_rate_control_init() functions
were never called because the rtl83xx_setup_qos() always returned after the
QoS configuration
Fixes: dc9cc0d3e2 ("realtek: add QoS and rate control")
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20637
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
symtom: macs not properly incremented (all macs the same)
solution: set correct offset to mac location
Signed-off-by: Scott Mercer <TheRootEd24@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20664
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The BPi-R4 Lite is a WiFi-7 router board based on the MT7987 SoC.
Specification :
- SOC: Mediatek MT7987A (4x Cortex-A53
- RAM: 2GB
- Flash: 32MB SPI NOR, 256MB SPI NAND, 8GB eMMC
- Switch: MediaTek MT7531AE
- Ports : 4x LAN (1G), 1x SFP (via MT7531), 1x WAN (2.5G)
- Buttons : Reset & WPS/Mesh
- LEDs : Status (PWM), SFP
- USB: on-board VIA VL817 USB3.1/USB2.0 hub
* 1 - mPCIe B (SIM3)
* 2 - NGFF-KEYB (SIM1)
* 3 - USB-A connector
* 4 - mPCIe A (SIM4)
- mPCIe: 1x 8GT/s x2 or 2x 8GT/s x1 (configurable via bootloader)
- RTC: PCF8563
- mikroBUS socket with SPI, I2C and full UART
- on-board HT42B534 USB-to-serial for Type-C console port
- Power: USB Type-C PD 20V, or DC via barrel connector or JST-VH 3.96
Installation:
Uncompress *sdcard.img.gz and write to microSD card, eg. using 'dd'.
Use bootloader menu on the serial console to install SPI-NAND or SPI-NOR,
once installed to SPI-NAND you can use the bootloader menu to install to
eMMC. See instructions for BananaPi R3 for details.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Import and clean DT and DT-overlay files from MediaTek's SDK to build
an image with various DT-overlays for the MT7987 reference board.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Import patches to use cpufreq voltage calibration data from the efuse on
MT7988, and add support for MT7987.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
The MT7987 has two LVTS thermal sensors, one covering all CPU cores,
and one for the built-in 2.5GE PHY.
Add support for MT7987 to the LVTS thermal driver.
Thanks to Chad Monroe of Adtran for providing cleaned up patches for
Linux 6.6 which have been ported to Linux 6.12.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Compared to MT7988 (NETSYSv3) the Ethernet Frame Engine of MT7987
has been slighly updated (NETSYSv3.1), among other things the packet
scheduler (shaper) has apparently been reworked.
Import patches for basic support of the Ethernet Frame Engine of the
MT7987 SoC.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
The MT7987 is mostly a stripped-down low-pin-count version of the
MT7988 without the 10GBit/s SerDes. Most existing drivers can be reused.
Import to-be-sent-upstream patches doing all the groundwork for
basic support for the MT7987 SoC, adding clk, pinctrl and pwm support.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Currently the detection of external-data FIT images works by checking
if the FIT structure is more than 4 kiB. However, for boards with lots
of different DT-overlays and configurations the FIT structure can
exceed 4 kiB which results in the FIT splitter to fail detecting the
rootfs.
Increase the threshold for external-data FIT to 512 kiB as there aren't
any kernel images smaller than that, and FIT structure less than 512 kiB
will always be an external-data FIT.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Make functions in b53 static and add kernel
patch to fix prototype build errors
Signed-off-by: Kyle Hendry <kylehendrydev@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20653
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
After switching to the 6.12 kernel, time to remove 6.6 support.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20614
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Linux 6.12 has been validated on Layerscape platforms, including NXP
reference boards and multiple custom designs. Tests covered system
boot, networking, storage, and common peripherals, with no regressions
observed.
Enable 6.12 as the default to continue broader testing and integration.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20614
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
On the LS1012A-FRDM both PHY reset pins are tied to GPIO1_23.
Up to Linux 6.6, pinctrl did not touch this GPIO and the reset
line remained in the state set by U-Boot. Starting from 6.12,
the kernel requires explicit configuration of this pin, otherwise
the PHYs fail to be detected.
This adds a gpio-hog node to ensure the reset line stays asserted,
fixing PHY detection on boot.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20614
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Drop support for kernel 6.6 as now kernel 6.12 is set as default kernel
version.
Link: https://github.com/openwrt/openwrt/pull/20644
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Move the ipq806x target to kernel 6.12 by default as every kernel bump
problem has been handled.
Link: https://github.com/openwrt/openwrt/pull/20644
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The Google OnHub doesn't init the SMEM in SBL causing the CPUFreq driver
to fail probe. This is caused by the fact that new CPUFreq driver makes
use of SMEM to identify the SoC variant and on Google OnHub this is not
available.
Backport patch to detect this state and fallback to compatible
matching fixing the CPUFreq driver.
Link: https://github.com/openwrt/openwrt/pull/20587
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
This device is very similar to the already supported XGS1210-12 A1. For
now, only revision A1 is supported (not marked on the label).
Hardware:
- RTL9302B SoC
- 16 MiB NOR flash
- 128 MiB DDR3 SDRAM
- 8x 1G RJ45 (RTL8218D)
- 2x 2.5G RJ45 (2x RTL8226)
- 2x SFP+ (supporting 1G/2.5G/10G)
- 3.3V UART serial (115200 baud 8N1) on the right side of the case
(from bottom to top: GND, RX, TX, VCC)
It is originally an unmanaged switch, so there are a few differences:
- No reset button
- Different partition layout: There is some reserved space in the middle
of the flash which might be used by the bootloader for flash testing.
The remaining space in between is used for OpenWrt using mtd-concat.
The largest contiguous area is at the beginning, allowing a maximum
kernel size of 7 MiB.
- No individual MAC address: This device ships with an empty U-Boot
environment. When an OpenWrt squashfs image is booted for the first
time, a random MAC address will be written to the environment (but
only if the environment has been initialized from the bootloader
before and contains the default MAC address).
Steps to boot initramfs image via network:
- Configure a TFTP server to provide the OpenWrt initramfs image
- Connect to device using serial (see hardware information above)
- Power on the device and enter U-Boot using Esc when prompted
- Run the following commands (adjust as necessary):
# rtk network on
# tftpboot 0x84f00000 192.168.1.100:openwrt-xgs1010-initramfs.bin
# bootm
Installation on flash:
- Boot initramfs image as described above
- Now is a good time to create a backup of all flash partitions! You'll
need this if you want to revert to the unmanaged factory firmware at
some point.
- Use sysupgrade to install OpenWrt
- After restart enter U-Boot again and set the boot command:
# setenv bootcmd 'rtk network on; bootm 0xb4900000'
# saveenv
# run bootcmd
Note: The command "rtk network on" is only needed because the drivers
currently rely on some setup by the bootloader (without this the RJ45
ports don't work). If the drivers improve in the future, it should be
removed (i.e. change the boot command to "bootm 0xb4900000").
Reverting to factory firmware:
- Write back your backup of the firmware partition (or write just the
fwconcat1 partition, and erase the other two fwconcat partitions)
- Change the boot command back to "boota" (or just erase the u-boot-env
partition so the default gets used)
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/20469
Signed-off-by: Robert Marko <robimarko@gmail.com>
This is a preparation for adding support for XGS1010-12, which is almost
identical to XGS1210-12, with some small differences (partition layout,
missing reset key).
In addition to moving the common parts to a new file, also simplify the
definition of the 2.5G PHYs to reduce duplication. With this change, the
revision-specific files only have to specify the SMI addresses.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/20469
Signed-off-by: Robert Marko <robimarko@gmail.com>
After having moved RTL93XX SerDes configuration from PHY to PCS driver,
the DSA driver doesn't need to know about SerDes explicitly anymore.
Although RTL83XX SerDes is still partly managed within the DSA driver,
it doesn't make use of the sds_num property/field. RTL93XX was the only
user of this right now.
Thus, we can just remove the remaining 'sds_num' code which doesn't
serve any purpose anymore.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20577
Signed-off-by: Robert Marko <robimarko@gmail.com>
RTL93XX SerDes is entirely managed through the PCS driver and not
treated as PHYs anymore. Thus, remove the leftovers from the DSA driver.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20577
Signed-off-by: Robert Marko <robimarko@gmail.com>
Drop the now unused SerDes code for RTL930X from rtl83xx-phy driver as
the SerDes is completely managed by the PCS driver.
This marks a breaking point because RTL930X SerDes is no longer treated
as a regular PHY device.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20577
Signed-off-by: Robert Marko <robimarko@gmail.com>
RTL93XX reached the point where the SerDes' are no longer treated as
regular PHYs. Instead, they are managed by the dedicated PCS driver.
Thus, all device tree definitions should follow this change.
Remove the pseudo-PHYs for the SerDes (so far usually defined with macro
INTERNAL_PHY) and corresponding 'phy-handle's from all SFP ports. This
removes a long-lasting confusion from our Realtek driver(s).
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20577
Signed-off-by: Robert Marko <robimarko@gmail.com>
When Realtek SerDes is completely handled by PCS, it is not treated as
a regular PHY anymore. Thus, we should be able to drop the currently
used pseudo-PHYs and phy-handles for ports which just use the SerDes as
PCS but have no PHY attached.
Allow to drop the phy-handle from switch port definitions if there is a
pcs-handle defined by relaxing several checks in the DSA driver.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20577
Signed-off-by: Robert Marko <robimarko@gmail.com>
Check for and handle an error which may be returned by rtpcs_create in
various cases.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20577
Signed-off-by: Robert Marko <robimarko@gmail.com>
The code to add bootstrapping for 10G-QXGMII on RTL930X broke the only
devices which are using 10G-QXGMII on RTL930X (Plasma Cloud PSX8+PSX10) in
OpenWrt. It is currently unknown what other changes are pending to get this
correctly working. But both the `rtpcs_930x_sds_usxgmii_config()` call and
the write of the "magic" SerDes values in the patching process break the
SerDes connected to the RTL8224 PHYs.
The Plasma Cloud PSX8+PSX10 devices get their RTL8224 and the 10G-QXGMII
SerDes bootstrapped directly by u-boot.
Fixes: dca20f91ea ("realtek: add serdes patch for 10G_QXGMII")
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20588
Signed-off-by: Robert Marko <robimarko@gmail.com>
Package driver for Broadcom V3D 3.x or newer GPUs.
SoCs supported include the BCM2711, BCM7268 and BCM7278.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Align the sorting of cases with other targets.
Signed-off-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20603
Signed-off-by: Robert Marko <robimarko@gmail.com>
Merge identical case in base-files.
Signed-off-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20603
Signed-off-by: Robert Marko <robimarko@gmail.com>
This removes the obsolete trailing whitespaces from all base-files cases
to be in line with other targets.
Signed-off-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20603
Signed-off-by: Robert Marko <robimarko@gmail.com>
Switch the mac lookup to NVMEM on UBI layout and add label-mac
Signed-off-by: Steffen Förster <nemesis@chemnitz.freifunk.net>
Link: https://github.com/openwrt/openwrt/pull/20612
Signed-off-by: Robert Marko <robimarko@gmail.com>
Fix Totolink X6000R image failing to upgrade via sysupgrade due to an
incorrect upgrade case. The fallback upgrade path used the NAND upgrade
routine, which caused the "layout volume not found" error on NOR flash
devices. By adding a specific case for this board, sysupgrade now uses
`default_do_upgrade`, which is compatible with the NOR flash layout.
Fixes: 7cd10ad
Signed-off-by: Ayra Hikari <ayrahikari@linuxmail.org>
Since 6b43a52171, the PHY is using interrupts instead of polling. It
turned out that the interrupt number is wrong and the WAN port doesn't
work. This commit fixes this bug.
Fixes: 6b43a52171 ("mediatek: mt7622: add the missing phy interrupt-parent for WAX206")
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Commits d205878ede and 46cf10771a relabeled the supported Zyxel devices
from v1/v2 to A1/B1, but board setup files were overlooked.
Fixes: d205878ede ("rtl838x: rename GS1900 series v1/v2 to A1/B1")
Fixes: 46cf10771a ("rtl839x: rename GS1900 series v1/v2 to A1/B1")
Signed-off-by: Stijn Segers <foss@volatilesystems.org>
Link: https://github.com/openwrt/openwrt/pull/20590
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add support to the airoha target for the OpenWrt-specific DT property
`openwrt,netdev-name`. In particular, this is for interfaces under
non-DSA `airoha_eth` interfaces.
This will avoid conflicts with upstream code[1]; and maintain forward
compatibility with OpenWrt configurations if/when `airoha_eth` becomes
a full DSA driver.
[1] https://lore.kernel.org/netdev/20240709124503.pubki5nwjfbedhhy@skbuf/
Borrowed from d4d6c48 (mediatek: filogic: support openwrt,netdev-name for renaming interfaces)
Signed-off-by: Kenneth Kasilag <kenneth@kasilag.me>
Link: https://github.com/openwrt/openwrt/pull/20475
Signed-off-by: Robert Marko <robimarko@gmail.com>
The device is the little brother of the already supported ASUS Lyra but
with the flash configuration/layout of the RT-AC58U.
Hardware
--------
SOC: Qualcomm IPQ4019
FLASH: 2MB (Macronix MX25L1606E)
128MB (GigaDevice GD5F1GQ4UCYIG)
RAM: 256MB (Nanya NT5CC128M16IP-DI)
WIFI: Qualcomm IPQ4019
BT: Atheros AR3012-BL3D
ETH: 1x WAN, 1x LAN
LED: 1 RBG LED
BTN: WPS, Reset
UART: 115200 8N1 (square pin = VCC) VCC-TX-RX-GND
MAC addresses
-------------
LAN 2.4G + 1
WAN 2.4G + 3
2.4G Label MAC (stored in factory offset 0x1006)
5G 2.4G + 2 (stored in factory offset 0x5006)
Installation
------------
SSH
---
1. Reset the device, setup and enable SSH.
2. Transfer initramfs.itb to /tmp on the device.
3. SSH into the router, credentials are the same as in the web ui.
4. Write initramfs to linux partition:
mtd-write -d linux -i initramfs.itb
5. Reboot and wait for OpenWrt to boot.
6. Transfer sysupgrade.bin to /tmp on the device.
7. SSH into the router, user root, no pw.
8. Delete jffs2 ubi partition:
ubirmvol /dev/ubi0 --name=jffs2
9. Flash OpenWrt:
sysupgrade -n sysupgrade.bin
Signed-off-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20573
Signed-off-by: Robert Marko <robimarko@gmail.com>
This reverts commit f795ecc0dd.
Now that AUTORELEASE has been dropped from main, we can go back on
shallow clone it for faster SDK usage.
Link: https://github.com/openwrt/openwrt/pull/20586
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Datasheet claims this register bit is supposed to be set by default,
however it was found in practice to not be, and OEM drivers would set
this bit at the same time.
Signed-off-by: Richard Huynh <voxlympha@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20465
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Fix typo in register for the serdes global config.
Fixes: ddb0cd276c ("kernel: rtl8261n: add support for Serdes TX swap")
Signed-off-by: Richard Huynh <voxlympha@gmail.com>
[ add commit description ]
Link: https://github.com/openwrt/openwrt/pull/20465
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Backport upstream minor fixed for NPU handling that might result in
kernel panic or handle leak.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Add missing leds and network board files for EN7581 SoC.
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
[ drop reference to downstream 10g RFB board ]
Link: https://github.com/openwrt/openwrt/pull/20556
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Similar to e92b153e99 ("mediatek: introduce KERNEL_LOADADDR to Device/Default template"),
let's move the default loadaddr to Device/Default.
What's more, use 0x80200000 instead of the SDK default value 0x80088000
to avoid the following error which may overwrite TZ memory and cause crash:
[ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
[ 0.000000] OF: reserved mem: Reserved memory: failed to reserve memory for node 'atf@80000000': base 0x0000000080000000, size 2 MiB
Signed-off-by: Ziyang Huang <hzyitc@outlook.com>
[ fix spelling mistake ]
Link: https://github.com/openwrt/openwrt/pull/20470
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Enable USB node on eMMC RFB board and disable USB2 3.0 port to make the
3rd PCIe line correctly work.
This is needed to prevent the xHCI driver to mess with PCIe by
configuring the USB2 3.0 port. Port will still be detected but won't be
configureed by the driver and won't have PHY to configure for.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The 3rd PCIe line use the USB2 serdes for PCIe operation. Correctly set
it to the DT node so that the mode can be correctly set in the PHY
driver.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Add pending patch for USB support on AN7581 SoC. This is also required
to make operational the 3rd PCIe line that use the USB2 Serdes for PCIe
operations.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Fix regression from back when support for RTL930x was added.
While at it replace 0x8000 by BIT(15).
Fixes: 27029277f9
Tested-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Signed-off-by: Felix Baumann <felix.bau@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20549
Signed-off-by: Robert Marko <robimarko@gmail.com>
Remove SerDes initialization/configuration calls from the DSA driver in
'rtl93xx_phylink_mac_config' and let our PCS driver setup the SerDes now
that the driver is able to do that.
Adjust some details in rtl93xx_phylink_mac_config to ensure the MAC is
properly disabled MAC before configuring the SerDes. This was done
within the SerDes code before.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20539
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use regmap to access registers in the global register space so we don't
have to use the old macros sw_r32/sw_w32 anymore.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20539
Signed-off-by: Robert Marko <robimarko@gmail.com>
Import SerDes configuration code from PHY driver into the PCS driver.
Only do mandatory adjustments, rename the function to adhere to the
naming scheme, adjust all SerDes access calls.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20539
Signed-off-by: Robert Marko <robimarko@gmail.com>
This fixes the sysupgrade image generation for the LBR20 as before
updating resulted in a brick which needed to be recovered using
nmrpflash.
UART log of a bricked unit:
Loading DNI firmware for checking...
Loading firmware 1 ...
NAND read: device 0 offset 0xa600000, size 0x20000
131072 bytes read: OK
NAND read: device 0 offset 0xa600000, size 0x380000
3670016 bytes read: OK
rootfs imge header corrupted !
Loading firmware 2 ...
NAND read: device 0 offset 0xa600000, size 0x20000
131072 bytes read: OK
NAND read: device 0 offset 0xa600000, size 0x380000
3670016 bytes read: OK
rootfs imge header corrupted !
Comparing the partition contents of a bricked and a working unit showed
that on the bricked one the fake uImage header was missing. The UBI
partition also showed significant changes. Both are fixed when the
base DniImage receipt is used.
Signed-off-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20558
Signed-off-by: Robert Marko <robimarko@gmail.com>
This aligns the LED behaviour with other Orbi devices. Orbi devices have
multiple RBG LEDs at the top of the device and two status LEDs at the
back next to the barrel jack.
The current behaviour of other Orbi devices is to use the multi-color
LEDs at the top for status indication and the green/red LEDs at the back
for running/panic-indication. This matches the vendor behaviour except
the color choice.
Other devices use green as running, blue on upgrade, red on failsafe and
white on bootup, so this aligns the LBR20 behaviour to the rest.
Signed-off-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20558
Signed-off-by: Robert Marko <robimarko@gmail.com>
This will remove the ethernet0 alias and TODO as setting the LAN MAC via
nvmem to gmac0 will set the correct mac to the switch.
Signed-off-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20558
Signed-off-by: Robert Marko <robimarko@gmail.com>
Some SoC might use the Serdes for the second USB port as a 3rd PCIe
line (with the SSTR register correctly setup).
Add the node for the 3rd PCIe card and enable for the eMMC RFB board.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
gpio-leds were not working on F@ST3864OP before was merged.
This pull request adds definitions for all LEDs, including the previously
non-working WAN LEDs.
Signed-off-by: Hang Zhou <929513338@qq.com>
Link: https://github.com/openwrt/openwrt/pull/20533
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
In Realtek implementation USXGMII is divided in submodes:
- USXGMII_SX: 10G single link, equivalent of PHY_INTERFACE_MODE_USXGMII
- USXGMII_DX: 10G two links (2*5G ?),
- USXGMII_QX: 10G four links, presumably 4*2.5G, used with the RTL8224,
equivalent of PHY_INTERFACE_MODE_10G_QXGMII.
This CL adds the 10_GQXGMII modes to the RTL930x implementation. In
particular the "mode set" function is extended to support both simple
mode set, and force mode set depending on the mode according to
dal_longan_sds_mode_set [1].
[1] https://github.com/ddejean/dms-1250-oss-release/blob/main/sdk/sdk_rtk_switch/rtk-sdk/src/dal/longan/dal_longan_sds.c#L1746
Signed-off-by: Damien Dejean <dam.dejean@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20472
Signed-off-by: Robert Marko <robimarko@gmail.com>
Fix the GPIO assignment of RX-LOS and TX-DISABLE for all SFP ports. Both
were actually swapped when adding support for the device. Apparently,
this didn't cause any issues.
Fixes: 62d50fb196
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20532
Signed-off-by: Robert Marko <robimarko@gmail.com>
The OnHub bootloader tries to patch the calibration directly into the
device tree, but it uses constant paths that look like this:
static const char *dt_path = "soc/pci@%8.8x/pcie@0/ath10k@0,0";
https://chromium.googlesource.com/chromiumos/platform/depthcharge/+/refs/heads/firmware-storm-6315.B/src/board/storm/wifi_calibration.c#69
These paths have changed in recent kernels, so we need to adapte.
The CONFIG_GOOGLE_VPD kernel module (provided by kmod-google-firmware)
is present on OnHub, and provides alternative means to locate this
information, in /sys/firmware/vpd/ro/wifi_base64_calibration{0,1,2}. Use
that instead.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20477
Signed-off-by: Robert Marko <robimarko@gmail.com>
Backport a patch fixing a kernel panic on airoha_hw_init fail. This
should better handle scenario with NPU load Probe deferring.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Backport cleanup patch for Airoha Ethernet patch to permit easier
backport in the future.
Automatically refresh all affected patch.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Add pending patch to make address some workaround needed to make the
Aeonsemi AS21xxx PHY working on the Airoha AN7581/AN7583 board.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Airoha AN7581 eMMC RFB board mount 2 Aeonsemi AS21xxx PHY. One is
usually connected to GDM4 and the other is optionally connected to GDM2.
Add the relevant nodes to support the one connected to GDM4.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Userspace handling is deprecated.
Move calibration for pcie node out of dtsi. calibration size for ath10k
and ath9k differs.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/16231
Signed-off-by: Robert Marko <robimarko@gmail.com>
Align the sorting of cases with other targets.
Signed-off-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20518
Signed-off-by: Robert Marko <robimarko@gmail.com>
Merge some identical cases in base-files.
Signed-off-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20518
Signed-off-by: Robert Marko <robimarko@gmail.com>
This changes the use of spaces to tabs in all base-files to be in line
with other targets.
Signed-off-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20518
Signed-off-by: Robert Marko <robimarko@gmail.com>
This removes the obsolete trailing whitespaces from all base-files cases
to be in line with other targets.
Signed-off-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20518
Signed-off-by: Robert Marko <robimarko@gmail.com>
Pack the BL2 and BL31+U-Boot artifacts as Airoha AN7581 is currently
supported in upstream U-Boot and bootloader files can be used for
unfused boards.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Since ddf94f7489 and 4a5de35dba, a SerDes is configured by the PCS
driver. All code from PHY and DSA related to this has been imported and
adjusted into the PCS driver. Thus, remove the unused code from the PHY
driver now.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20494
Signed-off-by: Robert Marko <robimarko@gmail.com>
Backport additional patch required for NPU support of Airoha AN7583.
These are specific for the NPU module with some minor fixes and to adds
upport for loading the specific Airoha AN7583 NPU firmware.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Add relevant nodes for NPU support for Airoha AN7583 and enable the
kernel config to enable support in the Airoha Ethernet driver.
NPU firmware is scheduled to be upstreamed to linux-firmware and will be
added once present upstream.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Fix the current image Makefile for Airoha AN7583 by dropping the
artifacts entry for bootloader and add default PKG for the PHY mounted
on the RFB boards.
The artifacts for the bootloader will be readded later once ATF-A
support will be pushed mainline.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
While adding support for Airoha AN7583, it was forget to push the EMMC
DTS while defining the variant in the image Makefile.
Add the missing DTS to fix image creation error.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
On the Airoha AN7583 EVB there are 2 Aeonsemi AS21xxx PHY but only the
one connected to Serdes Ethernet is usable as the other connected to
Serdes PON is not actually HW connected (as the serdes is connected to
the BOSA port)
Add comments and disable the relevant PHY.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
This commit changes the Meraki MR33 and MR74 device trees to use nvmem
for ART calibration.
The WiFi BDF was moved from insect-common.dtsi to the respective
device files in preparation for additional insect-family devices being added.
Signed-off-by: Hal Martin <hal.martin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20474
Signed-off-by: Robert Marko <robimarko@gmail.com>
Userspace handling is deprecated.
Use ath9k LED instead of specifying a generic one.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/16286
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Userspace handling is deprecated.
Use ath9k LED binding to avoid generic LED usage.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/16286
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This board is also as known as E-Life ETR631-T/ETR635-U.
Hardware specification:
SoC: MediaTek MT7981B 2x A53
Flash: 128 MB SPI-NAND
RAM: 256MB DDR3
Ethernet: 4x 10/100/1000 Mbps
Switch: MediaTek MT7531AE
WiFi: MediaTek MT7976C
Button: Reset, Mesh
Power: DC 12V 1A
Gain telnet access:
1. Login into web interface, and download the configuration.
2. Uncompress the configuration:
* Enter fakeroot if you are not login as root.
tar -zxf <filename>.tar.gz
3. Edit 'etc/passwd', remove root password: 'root::1:0:99999:7:::'.
4. Edit 'etc/rc.local', insert telnetd command before 'exit 0':
( sleep 3s; telnetd; ) &
5. Repack the configuration:
tar -zcf backup.tar.gz etc/
6. Upload new configuration via web interface, now you can connect to
KOMI A31 via telnet.
Flash instructions:
1. Connect to KOMI A31, backup everything, especially 'Factory' part.
2. Write new BL2:
mtd write openwrt-mediatek-filogic-konka_komi-a31-preloader.bin BL2
3. Write new FIP:
mtd write openwrt-mediatek-filogic-konka_komi-a31-bl31-uboot.fip FIP
4. Set static IP on your PC:
IP 192.168.1.254/24, GW 192.168.1.1
5. Serve OpenWrt initramfs image using TFTP server.
6. Cut off the power and re-engage, wait for TFTP recovery to complete.
7. After OpenWrt has booted, perform sysupgrade.
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/20357
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Allows us a bit more headroom flash wise and access to more recent
compression algorithms.
Signed-off-by: Stijn Segers <foss@volatilesystems.org>
Link: https://github.com/openwrt/openwrt/pull/20445
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Drop config and patches for Linux 6.6.
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Link: https://github.com/openwrt/openwrt/pull/20468
Signed-off-by: Nick Hainke <vincent@systemli.org>
Switch to Linux kernel 6.12.
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Link: https://github.com/openwrt/openwrt/pull/20468
Signed-off-by: Nick Hainke <vincent@systemli.org>
Backport upstream patch for AN7583 Ethernet support. While at it also
backport some additional fixes required to apply the AN7583 patches
cleanly.
Refresh all affected patch automatically (aside from the XSI patch that
changed the implementation)
Link: https://github.com/openwrt/openwrt/pull/20489
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Backport phylink patches for PCS/PHY caps OPs. This makes it easier to
align future generic PCS patch and permit supporting special PHY that
needs specific tune if "in-band" mode is enabled (for example Aeonsemi
PHYs)
This is also mainly using the upstream version of the Mediatek patch
739-net-add-negotiation-of-in-band-capabilities.
All affected patch automatically refreshed.
Link: https://github.com/openwrt/openwrt/pull/20461
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Now that we have a board file, add calibration variant for TP-Link
Archer C60 v2 and add ipq-wifi package for it.
Tested-by: Semih Baskan <strstgs@gmail.com>
Signed-off-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20496
Signed-off-by: Robert Marko <robimarko@gmail.com>
L3 Offloading caused DHCP packets to be dropped at hardware level
And potentially buggy route implementation can cause a crash
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20208
Signed-off-by: Robert Marko <robimarko@gmail.com>
The RTL931x is not supporting L3 offloading at the moment. To avoid crashes
when using this switch, simply disable L3 offloading completely.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20208
Signed-off-by: Robert Marko <robimarko@gmail.com>
a33d59f7af (2025-10-14) restored dts files for kernel 6.6 to files-6.6
after the preceding 15fa59c41f moved files-6.6 to files-6.12 to be
used by the new testing kernel, 6.12. This restoration omitted
1a3f05eb2b (2025-10-08), which fixed important aspects of the wifi
device definitions in qcom-ipq8064-eax500.dtsi and
qcom-ipq8064-unifi-ac-hd.dts.
The 1a3f05eb2b fix persisted into the 6.12 dts files. This change now
restores it for 6.6. Note that ipq806x is currently using kernel 6.6 for
most purposes, as 6.12 is only in testing status for this target.
This change was prepared with `git diff
a33d59f7af8f:target/linux/ipq806x/files-6.6
15fa59c41f0d^:target/linux/ipq806x/files-6.6`. This identified
c186d17fa5 (2025-10-08) as another change that was not present in the
restored files-6.6, but it has since been superseded by 2a709d108e
(2025-10-20), so no action is necessary to restore it. There were no
diffs present between these revisions in config-6.6 or patches-6.6,
which were also moved and restored in the 6.12 bring-up.
Signed-off-by: Mark Mentovai <mark@mentovai.com>
Cc: Shiji Yang <yangshiji66@outlook.com>
Cc: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20464
Signed-off-by: Robert Marko <robimarko@gmail.com>
SQUASHFS_DECOMP_MULTI_PERCPU is selected by
SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU, so add it.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://github.com/openwrt/openwrt/pull/20140
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
